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under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer description 1 ------table of contents------ description the m30218 group of single-chip microcomputers are built using the high-performance silicon gate cmos process using a m16c/60 series cpu core and are packaged in a 100-pin plastic molded qfp. these single-chip microcomputers operate using sophisticated instructions featuring a high level of instruction efficiency. with 1m bytes of address space, they are capable of executing instructions at high speed. they also feature a built-in multiplier and dmac, making them ideal for controlling musical instruments, house- hold appliances and other high-speed processing applications. the m30218 group includes a wide range of products with different internal memory types and sizes and various package types. features ? basic machine instructions ............. compatible with the m16c/60 series ? memory capacity ............................ rom / ram (see figure memory expansion) ? shortest instruction execution time . 100ns (f(x in )=10mhz) ? supply voltage ................................ 4.0v to 5.5v (f(x in )=10mhz) 2.7v to 5.5v (f(x in )=3.5mhz)(note) ? interrupts ........................................ 19 internal and 6 external interrupt sources, 4 software ? multifunction 16-bit timer ................ timer a x 5, timer b x 3 ? fld conrtoller ................................. total 56 pins (high-breakdown-voltage p-channel open-drain output : 52pins) ? serial i/o ......................................... 2 channels for uart or clock synchronous, 1 channels for clock synchronous (max.256 bytes automatic transfer function) ? dmac ............................................. 2 channels (triggers: 15 sources) ? a-d converter ................................. 10 bits x 8 channels ? d-a converter ................................. 8 bits x 2 channels ? crc calculation circuit ................... 1 circuit ? watchdog timer .............................. 1 pin ? programmable i/o .......................... 48 pins ? high-breakdown-voltage output ...... 52 pins ? clock generating circuit .................. 2 built-in clock generation circuit (built-in feedback resistor, and external ceramic or quartz oscillator) note: only mask rom version. applications household appliances, office equipment, audio etc. timer ............................................................. 70 serial i/o ....................................................... 87 a-d converter ............................................. 114 d-a converter ............................................. 124 crc calculation circuit .............................. 126 programmable i/o ports ............................. 128 flash memory version ................................. 152 central processing unit (cpu) ..................... 10 reset ............................................................. 14 clock generating circuit ............................... 18 protection ...................................................... 26 interrupts ....................................................... 27 watchdog timer ............................................ 45 dmac ........................................................... 47 fld controller ............................................... 53 specifications written in this manual are believed to be accurate, but are not guaranteed to be en- tirely free of error. specifications in this manual may be changed for functional or performance improvements. please make sure your manual is the latest edition.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer description 2 pin configuration figures aa-1 show the pin configurations (top view). pin configuration (top view) figureaa-1. pin configuration (top view) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 M30218MC-XXXXFP p6 0 /fld0 p6 1 /fld1 p6 2 /fld2 p6 3 /fld3 p6 4 /fld4 p6 5 /fld5 p6 6 /fld6 p6 7 /fld7 p5 0 /fld8 v cc x in reset x out v ss cnv ss p8 6 /x cout p8 7 /x cin p9 0 /srdy2 p7 6 /ta3 in /ta1 out /clk1 p7 7 /ta4 in /ta2 out /cts1/rts1/clks1 p9 4 /s out 2 p9 5 /sclk21 p9 6 /da1/sclk22 p9 7 /da0/clk out /dim out p9 2 /sstb2 p9 3 /s in2 p7 3 /ta0 in /ta3 out p7 2 /tb2 in p9 1 /sbusy2 packa g e:100p6s-a v ee p10 7 /an7 p10 6 /an6 p10 5 /an5 p10 3 /an3 p10 2 /an2 p10 4 /an4 p10 1 /an1 av ss p10 0 /an0 v ref av cc p5 1 /fld9 p5 2 /fld10 p5 3 /fld11 p5 4 /fld12 p5 5 /fld13 p5 6 /fld14 p5 7 /fld15 p0 0 /fld16 p0 1 /fld17 p0 2 /fld18 p0 3 /fld19 p0 4 /fld20 p0 5 /fld21 p0 6 /fld22 v ss p0 7 /fld23 v cc p1 0 /fld24 p1 1 /fld25 p1 2 /fld26 p1 3 /fld27 p1 4 /fld28 p1 5 /fld29 p1 6 /fld30 p1 7 /fld31 p2 0 /fld32 p2 1 /fld33 p2 2 /fld34 p2 3 /fld35 p2 4 /fld36 p2 5 /fld37 p2 6 /fld38 p2 7 /fld39 p3 0 /fld40 p3 1 /fld41 p3 2 /fld42 p3 3 /fld43 p3 4 /fld44 p3 5 /fld45 p3 6 /fld46 p3 7 /fld47 p4 0 /fld48 p4 1 /fld49 p4 2 /fld50 p4 3 /fld51 p4 4 /t x d0/fld52 p4 5 /r x d0/fld53 p4 6 /clk0/fld54 p47/cts0/rts0/fld55 p7 5 /ta2 in /ta0 out /r x d1 p7 4 /ta1 in /ta4 out /t x d1 p7 1 /tb1 in p7 0 /tb0 in p8 5 /int5 p8 4 /int4 p8 3 /int3 p8 2 /int2 p8 1 /int1 p8 0 /int0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer description 3 block diagram figure aa-2 is a block diagram of the m30218 group. block diagram of the m30218 group figureaa-2. block diagram of m30218 group aaaa aaaa timer timer ta0 (16 bits) timer ta1 (16 bits) timer ta2 (16 bits) timer ta3 (16 bits) timer ta4 (16 bits) timer tb0 (16 bits) timer tb1 (16 bits) timer tb2 (16 bits) internal peripheral functions watchdog timer (15 bits) dmac (2 channels) d-a converter (8 bits x 2 channels) a-d converter (10 bits x 8 channels ) si/o2 (clock synchronous ) (256 bytes automatic transfer) system clock generator x in -x out x cin -x cout m16c/60 series16-bit cpu core i/o ports port p0 8 port p1 8 port p2 8 port p3 8 port p4 8 port p5 8 port p6 8 8 r0l r0h r1 h r1l r 2 r 3 a0 a1 fb r0l r0h r1h r1l r2 r3 a0 a1 fb registers isp usp stack pointer vector table intb crc arithmetic circuit (ccitt) (polynomial : x 16 +x 12 +x 5 +1) multiplier 8 8 8 port p10 port p9 port p8 port p7 aaaaaa a aaaa a a aaaa a a aaaa a aaaaaa memory rom (note 1) ram (note 2) (includes fldc,asi/o ram) sb flg pc program counter fluorescent display function (56 contorol pins) (52 high-breakdown-voltage ports) serial i/o uart/clock synchronous si/o (8 bits x 2 channels) note 1: rom size depends on mcu type. note 2: ram size depends on mcu type.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer description 4 rom ram p3, p4, p7 to p10 p0 to p2, p5, p6 ta0, ta1, ta2, ta3, ta4 tb0, tb1, tb2 uart0, uart1 si/o2 table aa-1. performance outline of m30218 group performance outline table aa-1 is a performance outline of m30218 group. item performance number of basic instructions 91 instructions shortest instruction execution time 100ns(f(x in )=10mhz) see figure memory expansion see figure memory expansion 8 bits x 6 8 bit x 5 16 bits x 5 16 bits x 3 (uart or clock synchronous) x 2 (clock synchronous) x 1 (with automatic transfer function) fluorescent display 56 pins a-d converter 10 bits x 8 channels d-a converter 8 bits x 2 dmac 2 channels (triggers :15 sources) crc calculation circuit 1 circuit (polynomial: x 16 + x 12 + x 5 + 1) watchdog timer 15 bits x 1 (with prescaler) interrupt 19 internal and 6 external sources, 4 software sources, 7 levels clock generating circuit 2 built-in clock generation circuits (built-in feedback resistor, and external ceramic or quartz oscillator) supply voltage 4.0 to 5.5v (f(x in )=10mhz) 2.7 to 5.5v (f(x in )=3.5mhz) (note) power consumption 18 mw (v cc =3v, f(x in )=5mhz) v cc -48v (output ports : p0 to p2, p5, p6, i/o ports : p3, p4 0 to p4 3 ) 0 to v cc (i/o ports :p4 4 to p4 7 , p7 to p10) - 18ma (p0 to p3, p4 0 to p4 3 , p5, p6) :high-breakdown-voltage, p-channel open-drain - 5ma (p4 4 to p4 7 , p7 to p10) 5ma (p4 4 to p4 7 , p7 to p10) operating ambient temperature C20 to 85 o c device configuration cmos silicon gate package 100-pin plastic mold qfp memory capacity i/o port output port multifunction timer serial i/o i/o withstand voltage output current i/o characteristics h l note: only mask rom version.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer description 5 mitsubishi plans to release the following products in the m30218 group: (1) support for mask rom version and flash memory version (2) memory capacity (3) package 100p6s : plastic molded qfp (mask rom version and flash memory version) figure aa-4. type no., memory size, and package figure aa-3. rom expansion ram size (byte) 12k 1k 512 M30218MC-XXXXFP m30218fcfp 128k rom size (byte) m30217ma-xxxxfp 5k 96k package type: fp : package 100p6s-a rom no. omitted for flash memory version rom capacity: 2 : 16k bytes 4 : 32k bytes 6 : 48k bytes 8 : 64k bytes a : 96k bytes c : 128k bytes memory type: m : mask rom version f : flash memory version type no. m 3 0 2 1 8 m c ? x x x x f p m16c/21 group m16c family shows ram capacity, pin count, etc (the value itself has no specific meaning) shows pull-down option type
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer pin description 6 pin description v cc , v ss cnv ss x in x out av cc av ss v ee p0 0 /fld 16 to p0 7 /fld 23 p1 0 /fld 24 to p1 7 /fld 31 p2 0 /fld 32 to p2 7 /fld 39 p3 0 /fld 40 to p3 7 /fld 47 p4 0 /fld 48 to p4 7 /fld 56 signal name power supply input cnv ss reset input clock input clock output analog power supply input pull-down power source output port p0 output port p1 output port p2 i/o port p3 i/o port p4 supply 2.7v(note1) to 5.5 v to the v cc pin. supply 0 v to the v ss pin. connect a bypass capacitor across the v cc pin and v ss pin. function connect it to the v ss pin. a ?? on this input resets the microcomputer. these pins are provided for the main clock generating circuit.connect a ceramic resonator or crystal between the x in and the x out pins. to use an externally derived clock, input it to the x in pin and leave the x out pin open. this pin is a power supply input for the a-d converter. connect this pin to v cc . this pin is a power supply input for the a-d converter. connect this pin to v ss . this is an 8-bit cmos output port and high-breakdown-voltage p- channel open-drain output structure. a pull-down resistor is built in between port p0 and v ee pin. at reset, this port is set to v ee level. p0 function as fld controller output pins as selected by software. this is an 8-bit output port equivalent to p0. pins in this port also function as fld controller output pins as selected by software. this is an 8-bit output port equivalent to p0. a pull-down resistor is not built in between p2 and v ee pin (note2). pins in this port also function as fld controller output pins as selected by software. this is an 8-bit i/o port. a pull-down resistor is not built in between p3 and v ee pin (note2). it has an input/output port direction register that allows the user to set each pin for input or output. this is low-voltage input level, and high-breakdown-voltage p-channel open-drain output structure. pins in this port also function as fld controller output pins as selected by software. this is an 8-bit i/o port equivalent to p3. this is low-voltage input level. p4 0 to p4 3 is high-breakdown-voltage p-channel open-drain output structure, p4 4 to p4 7 is cmos output. a pull-down resistor is not built in between p4(p4 0 to p4 3 ) and v ee pin (note2). pins in this port also function as fld controller output pins as selected by software. p4 4 to p4 7 also function as uart0 i/o pins as selected by software. when set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. pin name input input input output output output output i/o type analog power supply input input/output input/output reset v ref this pin is a reference voltage input for the a-d converter. input reference voltage input apply voltage supplied to pull-down resistors of ports p0 to p1,p5,p6. p5 0 /fld 8 to p5 7 /fld 15 output port p5 this is an 8-bit output port equivalent to p0. pins in this port also function as fld controller output pins as selected by software. output p6 0 /fld 0 to p6 7 /fld 7 output port p6 this is an 8-bit output port equivalent to p0. pins in this port also function as fld controller output pins as selected by software. output
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer pin description 7 pin description signal name function pin name i/o type input/output input/output i/o port p9 i/o port p10 p9 0 to p9 7 p10 0 to p10 7 this is an 8-bit i/o port equivalent to p7. when set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. p9 7 function as d-a converter output pins, clock output pins (same frequency of x in /8, x in /32 or x cin ) and dim signal output pin of fld controller as selected by software. p9 6 function as d- a converter output pins and clock i/o pin of serial i/o with automatic transfer as selected by software. p9 0 to p9 5 function as i/o pin of serial i/o with automatic transfer as selected by software. this is an 8-bit i/o port equivalent to p7. when set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. pins in this port also function as a-d converter input pins as selected by software. p7 0 to p7 7 i/o port p7 this is an 8-bit i/o port equivalent to p3. this is cmos input/output. when set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. p7 0 to p7 2 function as timerb0 to b2 input pins as selected by software. p7 3 function as timera0 i/o pin as selected by software. p7 4 to p7 7 function as timera1 to a4 i/o pins, and uart1 i/o pins as selected by software. input/output p8 0 to p8 7 i/o port p8 this is an 8-bit i/o port equivalent to p7. when set for input, the user can specify in units of four bits by software whether or not they are tied to a pull-up resistor. p8 0 to p8 5 function as external interrupt input pins as selected by software. p8 6 ,p8 7 function as sub-clock input pin as selected by software. in this case, connect a quarts oscillator between p8 6 (x out pin) and p8 7 (x cin pin) input/output note 1: supply 4.0v to 5.5v to the v cc pin in flash memory version. note 2: port p2 0 to p2 7 , p3 0 to p3 7 , and p4 0 to p4 3 can be selected whether pull-down resistors are built-in or not by the mask option specification. flash memor y version does not have this option.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer memory 8 operation of functional blocks the m30218 group accommodates certain units in a single chip. these units include rom and ram to store instructions and data and the central processing unit (cpu) to execute arithmetic/logic operations. also included are peripheral units such as timers, fld controller, serial i/o, d-a converter, dmac, crc calculation circuit, a-d converter, and i/o ports. the following explains each unit. memory figure ba-1 is a memory map of the m30218 group. the address space extends the 1m bytes from ad- dress 00000 16 to fffff 16 . from fffff 16 down is rom. for example, in the m30218mc-xxxfp, there is 128k bytes of internal rom from e0000 16 to fffff 16 . the vector table for fixed interrupts such as the reset are mapped to fffdc 16 to fffff 16 . the starting address of the interrupt routine is stored here. the address of the vector table for timer interrupts, etc., can be set as desired using the internal register (intb). see the section on interrupts for details. from 00400 16 up is ram. for example, in the m30218mc-xxxfp, there is 12k bytes of internal ram from 00400 16 to 033ff 16 . in addition to storing data, the ram also stores the stack used when calling subrou- tines and when interrupts are generated. (from 00400 16 to 004ff 16 is ram for sio2. from 00500 16 to 005df 16 is ram for fld.) the sfr area is mapped to 00000 16 to 003ff 16 . this area accommodates the control registers for periph- eral devices such as i/o ports, a-d converter, serial i/o, and timers, etc. any part of the sfr area that is not occupied is reserved and cannot be used for other purposes. the special page vector table is mapped to ffe00 16 to fffdb 16 . if the starting addresses of subroutines or the destination addresses of jumps are stored here, subroutine call instructions and jump instructions can be used as 2-byte instructions, reducing the number of program steps. figure ba-1. memory map 00000 16 xxxxx 16 fffff 16 00400 16 00500 16 005e0 16 yyyyy 16 aaaaaa a aaaa a aaaaaa internal rom area sfr area (for details, see figures ba-2 and ba-3) ram area for si/o2 ffe00 16 fffdc 16 fffff 16 undefined instruction overflow brk instruction address match single step watchdog timer reset special page vector table dbc type no. address xxxxx 16 m30218mc m30218fc e0000 16 address yyyyy 16 033ff 16 internal ram area ram area for fld (224 bytes) m30217ma e8000 16 017ff 16
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer memory 9 figure ba-2. location of peripheral unit control registers (1) 0000 16 0001 16 0002 16 0003 16 0004 16 0005 16 0006 16 0007 16 0008 16 0009 16 000a 16 000b 16 000c 16 000d 16 000e 16 000f 16 0010 16 0011 16 0012 16 0013 16 0014 16 0015 16 0016 16 0017 16 0018 16 0019 16 001a 16 001b 16 001c 16 001d 16 001e 16 001f 16 0020 16 0021 16 0022 16 0023 16 0024 16 0025 16 0026 16 0027 16 0028 16 0029 16 002a 16 002b 16 002c 16 002d 16 002e 16 002f 16 0030 16 0031 16 0032 16 0033 16 0034 16 0035 16 0036 16 0037 16 0038 16 0039 16 003a 16 003b 16 003c 16 003d 16 003e 16 003f 16 0040 16 0041 16 0042 16 0043 16 0044 16 0045 16 0046 16 0047 16 0048 16 0049 16 004a 16 004b 16 004c 16 004d 16 004e 16 004f 16 0050 16 0051 16 0052 16 0053 16 0054 16 0055 16 0056 16 0057 16 0058 16 0059 16 005a 16 005b 16 005c 16 005d 16 005e 16 005f 16 int1 interrupt control register (int1ic) timer b0 interrupt control register (tb0ic) timer b2 interrupt control register (tb2ic) timer a1 interrupt control register (ta1ic) timer a3 interrupt control register (ta3ic) uart0 transmit interrupt control register (s0tic) int2 interrupt control register (int2ic) int0 interrupt control register (int0ic) timer b1 interrupt control register (tb1ic) timer a0 interrupt control register (ta0ic) timer a2 interrupt control register (ta2ic) timer a4 interrupt control register (ta4ic) uart0 receive interrupt control register (s0ric) uart1 transmit interrupt control register (s1tic) uart1 receive interrupt control register (s1ric) dma1 interrupt control register (dm1ic) dma0 interrupt control register (dm0ic) a-d conversion interrupt control register (adic) dma0 control register (dm0con) dma0 source pointer (sar0) dma0 transfer counter (tcr0) dma0 destination pointer (dar0) dma1 control register (dm1con) dma1 source pointer (sar1) dma1 transfer counter (tcr1) dma1 destination pointer (dar1) watchdog timer start register (wdts) watchdog timer control register (wdc) processor mode register 0 (pm0) address match interrupt register 0 (rmad0) address match interrupt register 1 (rmad1) system clock control register 0 (cm0) system clock control register 1 (cm1) address match interrupt enable register (aier) protect register (prcr) processor mode register 1(pm1) int4 interrupt control register (int4ic) int3 interrupt control register (int3ic) int5 interrupt control register (int5ic) si/o automatic transfer interrupt control register (asioic) fld interrupt control register (fldic) 0340 16 0341 16 0342 16 0343 16 0344 16 0345 16 0346 16 0347 16 0348 16 0349 16 034a 16 034b 16 034c 16 034d 16 034e 16 034f 16 0350 16 0351 16 0352 16 0353 16 0354 16 0355 16 0356 16 0357 16 0358 16 0359 16 035a 16 035b 16 035c 16 035d 16 035e 16 035f 16 p3 fld/port switch register (p3fpr) p5 digit output set register (p5dor) toff2 time set register (toff2) fld data pointer (flddp) fld output control register (fldcon) p6 digit output set register (p6dor) p4 fld/port switch register (p4fpr) p2 fld/port switch register (p2fpr) tdisp time set register (tdisp) toff1 time set register (toff1) fld mode register (fldm) serial i/o2 automatic transfer data pointer (sio2dp) serial i/o2 control register 1 (sio2con1) serial i/o2 control register 2 (sio2con2) serial i/o2 register / transfer counter (sio2) serial i/o2 control register 3 (sio2con3)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer memory 10 figure ba-3. location of peripheral unit control registers (2) 0380 16 0381 16 0382 16 0383 16 0384 16 0385 16 0386 16 0387 16 0388 16 0389 16 038a 16 038b 16 038c 16 038d 16 038e 16 038f 16 0390 16 0391 16 0392 16 0393 16 0394 16 0395 16 0396 16 0397 16 0398 16 0399 16 039a 16 039b 16 039c 16 039d 16 039e 16 039f 16 03a0 16 03a1 16 03a2 16 03a3 16 03a4 16 03a5 16 03a6 16 03a7 16 03a8 16 03a9 16 03aa 16 03ab 16 03ac 16 03ad 16 03ae 16 03af 16 03b0 16 03b1 16 03b2 16 03b3 16 03b4 16 03b5 16 03b6 16 03b7 16 03b8 16 03b9 16 03ba 16 03bb 16 03bc 16 03bd 16 03be 16 03bf 16 dma1 request cause select register (dm1sl) dma0 request cause select register (dm0sl) uart0 transmit/receive mode register (u0mr) uart0 transmit buffer register (u0tb) uart0 receive buffer register (u0rb) uart1 transmit/receive mode register (u1mr) uart1 transmit buffer register (u1tb) uart1 receive buffer register (u1rb) timer a0 (ta0) timer a1 (ta1) timer a2 (ta2) timer b0 (tb0) timer b1 (tb1) timer b2 (tb2) count start flag (tabsr) one-shot start flag (onsf) timer a0 mode register (ta0mr) timer a1 mode register (ta1mr) timer a2 mode register (ta2mr) timer b0 mode register (tb0mr) timer b1 mode register (tb1mr) timer b2 mode register (tb2mr) up-down flag (udf) timer a3 (ta3) timer a4 (ta4) timer a3 mode register (ta3mr) timer a4 mode register (ta4mr) trigger select register (trgsr) uart0 bit rate generator (u0brg) uart0 transmit/receive control register 0 (u0c0) uart0 transmit/receive control register 1 (u0c1) uart1 bit rate generator (u1brg) uart1 transmit/receive control register 0 (u1c0) uart1 transmit/receive control register 1 (u1c1) uart transmit/receive control register 2 (ucon) crc data register (crcd) crc input register (crcin) clock prescaler reset flag (cpsrf) 03c0 16 03c1 16 03c2 16 03c3 16 03c4 16 03c5 16 03c6 16 03c7 16 03c8 16 03c9 16 03ca 16 03cb 16 03cc 16 03cd 16 03ce 16 03cf 16 03d0 16 03d1 16 03d2 16 03d3 16 03d4 16 03d5 16 03d6 16 03d7 16 03d8 16 03d9 16 03da 16 03db 16 03dc 16 03dd 16 03de 16 03df 16 03e0 16 03e1 16 03e2 16 03e3 16 03e4 16 03e5 16 03e6 16 03e7 16 03e8 16 03e9 16 03ea 16 03eb 16 03ec 16 03ed 16 03ee 16 03ef 16 03f0 16 03f1 16 03f2 16 03f3 16 03f4 16 03f5 16 03f6 16 03f7 16 03f8 16 03f9 16 03fa 16 03fb 16 03fc 16 03fd 16 03fe 16 03ff 16 port p0 (p0) port p1 (p1) port p2 (p2) port p3 (p3) port p3 direction register (pd3) port p4 (p4) port p4 direction register (pd4) port p5 (p5) port p6 (p6) port p7 (p7) port p7 direction register (pd7) port p8 (p8) port p8 direction register (pd8) port p9 (p9) port p9 direction register (pd9) port p10 (p10) port p10 direction register (pd10) pull-up control register 0 (pur0) pull-up control register 1 (pur1) a-d register 7 (ad7) a-d register 0 (ad0) a-d register 1 (ad1) a-d register 2 (ad2) a-d register 3 (ad3) a-d register 4 (ad4) a-d register 5 (ad5) a-d register 6 (ad6) a-d control register 0 (adcon0) a-d control register 1 (adcon1) d-a register 0 (da0) d-a register 1 (da1) d-a control register (dacon) a-d control register 2 (adcon2) flash memory control register 0 (fcon0) (note) flash memory control register 1 (fcon1) (note) flash command register (fcmd) (note) note: this re g ister is only exist in flash memory version.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer cpu 11 central processing unit (cpu) the cpu has a total of 13 registers shown in figure ca-1. seven of these registers (r0, r1, r2, r3, a0, a1, and fb) come in two sets; therefore, these have two register banks. (1) data registers (r0, r0h, r0l, r1, r1h, r1l, r2, and r3) data registers (r0, r1, r2, and r3) are configured with 16 bits, and are used primarily for transfer and arithmetic/logic operations. registers r0 and r1 each can be used as separate 8-bit data registers, high-order bits as (r0h, r1h), and low-order bits as (r0l, r1l). in some instructions, registers r2 and r0, as well as r3 and r1 can use as 32-bit data registers (r2r0, r3r1). (2) address registers (a0 and a1) address registers (a0 and a1) are configured with 16 bits, and have functions equivalent to those of data registers. these registers can also be used for address register indirect addressing and address register relative addressing. in some instructions, registers a1 and a0 can be combined for use as a 32-bit address register (a1a0). figure ca-1. central processing unit register aaaaaaa aaaaaaa h l b15 b8 b7 b0 r0 (note) aaaaaaa h l b15 b8 b7 b0 r1 (note) r2 (note) aaaaaaa aaaaaaa b15 b0 r3 (note) aaaaaaa b15 b0 a0 (note) aaaaaaa aaaaaaa b15 b0 a1 (note) aaaaaaa aaaaaaa b15 b0 fb (note) aaaaaaa b15 b0 data registers address registers frame base registers b15 b0 b15 b0 b15 b0 b15 b0 b0 b19 b0 b19 h l program counter interrupt table register user stack pointer interrupt stack pointer static base register flag register pc intb usp isp sb flg note: these re g isters consist of two re g ister banks. a a aa aa aa aa aa aa aaaaaa aaaaaa aa aa aa aa aa aa a a aa aa c d z s b o i u ipl
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer cpu 12 (3) frame base register (fb) frame base register (fb) is configured with 16 bits, and is used for fb relative addressing. (4) program counter (pc) program counter (pc) is configured with 20 bits, indicating the address of an instruction to be executed. (5) interrupt table register (intb) interrupt table register (intb) is configured with 20 bits, indicating the start address of an interrupt vector table. (6) stack pointer (usp/isp) stack pointer comes in two types: user stack pointer (usp) and interrupt stack pointer (isp), each config- ured with 16 bits. your desired type of stack pointer (usp or isp) can be selected by a stack pointer select flag (u flag). this flag is located at the position of bit 7 in the flag register (flg). (7) static base register (sb) static base register (sb) is configured with 16 bits, and is used for sb relative addressing. (8) flag register (flg) flag register (flg) is configured with 11 bits, each bit is used as a flag. figure ca-2 shows the flag register (flg). the following explains the function of each flag: ? bit 0: carry flag (c flag) this flag retains a carry, borrow, or shift-out bit that has occurred in the arithmetic/logic unit. ? bit 1: debug flag (d flag) this flag enables a single-step interrupt. when this flag is 1, a single-step interrupt is generated after instruction execution. this flag is cleared to 0 when the interrupt is acknowledged. ? bit 2: zero flag (z flag) this flag is set to 1 when an arithmetic operation resulted in 0; otherwise, cleared to 0. ? bit 3: sign flag (s flag) this flag is set to 1 when an arithmetic operation resulted in a negative value; otherwise, cleared to 0. ? bit 4: register bank select flag (b flag) this flag chooses a register bank. register bank 0 is selected when this flag is 0 ; register bank 1 is selected when this flag is 1. ? bit 5: overflow flag (o flag) this flag is set to 1 when an arithmetic operation resulted in overflow; otherwise, cleared to 0. ? bit 6: interrupt enable flag (i flag) this flag enables a maskable interrupt. an interrupt is disabled when this flag is 0, and is enabled when this flag is 1. this flag is cleared to 0 when the interrupt is acknowledged.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer cpu 13 figure ca-2. flag register (flg) ? bit 7: stack pointer select flag (u flag) interrupt stack pointer (isp) is selected when this flag is 0 ; user stack pointer (usp) is selected when this flag is 1. this flag is cleared to 0 when a hardware interrupt is acknowledged or an int instruction of software interrupt nos. 0 to 31 is executed. ? bits 8 to 11: reserved area ? bits 12 to 14: processor interrupt priority level (ipl) processor interrupt priority level (ipl) is configured with three bits, for specification of up to eight processor interrupt priority levels from level 0 to level 7. if a requested interrupt has priority greater than the processor interrupt priority level (ipl), the interrupt is enabled. ? bit 15: reserved area the c, z, s, and o flags are changed when instructions are executed. see the software manual for details. c a r r y f l a g d e b u g f l a g z e r o f l a g s i g n f l a g r e g i s t e r b a n k s e l e c t f l a g o v e r f l o w f l a g i n t e r r u p t e n a b l e f l a g s t a c k p o i n t e r s e l e c t f l a g r e s e r v e d a r e a p r o c e s s o r i n t e r r u p t p r i o r i t y l e v e l r e s e r v e d a r e a f l a g r e g i s t e r ( f l g ) c d z s b o i u i p l b 0 b 1 5
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer reset 14 reset there are two kinds of resets; hardware and software. in both cases, operation is the same after the reset. (see software reset for details of software resets.) this section explains on hardware resets. when the supply voltage is in the range where operation is guaranteed, a reset is effected by holding the reset pin level l (0.2v cc max.) for at least 20 cycles. when the reset pin level is then returned to the h level while main clock is stable, the reset status is cancelled and program execution resumes from the address in the reset vector table. figure da-1 shows the example reset circuit. figure da-2 shows the reset sequence. figure da-1. example reset circuit reset v cc 0.8v reset v cc 0v 0v 5v 5v 4.0v example when f ( x in ) = 10mhz and v cc = 5v . bclk address bclk 24cycles ffffc 16 ffffe 16 content of reset vector x in reset more than 20 cycles are needed (internal clock) (internal address s i g n a l ) figure da-2. reset sequence
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer reset 15 figure da-3. device's internal status after a reset is cleared x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. (1) (0004 16 ) processor mode register 0 (2) (0005 16 ) processor mode register 1 0 0 (3) (0006 16 ) system clock control register 0 1 00 00 10 0 (4) (0007 16 ) system clock control register 1 0 00 10 00 0 (5) (6) (0009 16 ) address match interrupt enable register 0 0 (7) (12) (13) (21) (22) (23) (20) (8) (0012 16 ) 0 (000f 16 ) watchdog timer control register 0 0? 0???? (0010 16 ) address match interrupt register 0 (0011 16 ) 00 16 00 16 0 0 0 (14) (9) (0014 16 ) address match interrupt register 1 (0015 16 ) (0016 16 ) 0 00 16 00 16 0 0 0 (002c 16 ) dma0 control register 00000?00 (003c 16 ) dma1 control register 00000?00 (0044 16 ) int3 interrupt control register 00?000 (15) (16) (17) (18) (19) (0048 16 ) int4 interrupt control register 00?000 (0049 16 ) int5 interrupt control register 00?000 (29) (30) (31) (32) (33) (34) (35) (36) (37) timer a0 interrupt control register timer a1 interrupt control register timer a2 interrupt control register timer a3 interrupt control register timer a4 interrupt control register timer b0 interrupt control register timer b1 interrupt control register (38) timer b2 interrupt control register (39) int0 interrupt control register (40) int1 interrupt control register (41) int2 interrupt control register (45) fldc mode register (46) fld output control register serial i/o 2 control register 2 (43) serial i/o 2 control register 3 (44) (42) serial i/o 2 control register 1 (47) tdisp time set register toff1 time set register toff2 time set register p2 fld/port switch register p4 fld/port switch register p6 digit output set register (0055 16 ) (0056 16 ) (0057 16 ) (0058 16 ) (0059 16 ) (005a 16 ) (005b 16 ) (005c 16 ) (005d 16 ) (005e 16 ) (005f 16 ) (0350 16 ) (0351 16 ) (0344 16 ) (0348 16 ) (0342 16 ) (0352 16 ) (0354 16 ) (0356 16 ) (0359 16 ) (035b 16 ) (035d 16 ) (035a 16 ) p3 fld/port switch register a-d conversion interrupt control register si/o automatic transfer interrupt control register fld interrupt control register (004e 16 ) ? 0 0 0 (004f 16 ) (0050 16 ) ? 0 0 0 ? 0 0 0 uart0 transmit interrupt control register uart0 receive interrupt control register (0051 16 ) (0052 16 ) ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 0 0 0 ? 000 00 ? 000 00 ? 000 00 p5 digit output set register (035c 16 ) (000a 16 ) protect register 0 0 0 (10) (11) (004b 16 ) dma0 interrupt control register ? 0 0 0 (004c 16 ) dma1 interrupt control register ? 0 0 0 uart1 transmit interrupt control register uart1 receive interrupt control register (0053 16 ) (0054 16 ) ? 0 0 0 ? 0 0 0 (24) (25) (26) (27) (28) 0 0 0 0 0 00 16 00 16 00 16 00 16 00 16 00 16 ff 16 ff 16 00 16 00 16 00 16 00 16 00 16
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer reset 16 figure da-4. device's internal status after a reset is cleared (0383 16 ) trigger select flag (0384 16 ) up-down flag (52) (51) (0396 16 ) timer a0 mode register (53) (0397 16 ) timer a1 mode register (54) (0398 16 ) timer a2 mode register (57) (039b 16 ) timer b0 mode register (58) (039c 16 ) timer b1 mode register (039d 16 ) timer b2 mode register (70) (55) (0399 16 ) timer a3 mode register (56) (039a 16 ) timer a4 mode register (0382 16 ) one-shot start flag (50) 00 16 00 16 0 00 16 00 16 00 16 00 16 00 16 0? 0000 00? 0000 00? 0000 (03ac 16 ) uart1 transmit/receive control register 0 (75) (03ad 16 ) uart1 transmit/receive control register 1 (76) (03b0 16 ) uart transmit/receive control register 2 (77) (03b8 16 ) dma0 cause select register (78) (03ba 16 ) dma1 cause select register (79) 0 (03a0 16 ) uart0 transmit/receive mode register (71) (03a4 16 ) uart0 transmit/receive control register 0 (72) (03a5 16 ) uart0 transmit/receive control register 1 (73) 00 16 000 1000 000 0010 0 0 (03a8 16 ) uart1 transmit/receive mode register (74) 00 16 000 1000 000 0010 0 0 00000 0 00 16 00 16 (03d4 16 ) a-d control register 2 (80) (03d6 16 ) a-d control register 0 (81) (03d7 16 ) a-d control register 1 (82) 0 000 0??? 0 00 16 0 00 0000 count start flag (0380 16 ) 00 16 0 (0381 16 ) clock prescaler reset flag (48) (49) x : nothing is mapped to this bit ? : undefined the content of other registers and ram is undefined when the microcomputer is reset. the initial values must therefore be set. (84) (85) (86) (03e7 16 ) port p3 direction register (87) (03ea 16 ) port p4 direction register (88) (89) (03ef 16 ) port p7 direction register (03f2 16 ) port p8 direction register (03f3 16 ) port p9 direction register (03f6 16 ) port p10 direction register (03fd 16 ) pull-up control register 0 (03fe 16 ) pull-up control register 1 00 16 00 16 00 16 00 16 00 16 00 16 00 16 frame base register (fb) address registers (a0/a1) interrupt table register (intb) user stack pointer (usp) interrupt stack pointer (isp) static base register (sb) flag register (flg) 0000 16 0000 16 00000 16 0000 16 0000 16 0000 16 0000 16 data registers (r0/r1/r2/r3) 0000 16 (03dc 16 ) d-a control register 00 16 (62) (61) (63) (64) (67) (68) (65) (66) (60) (59) (69) (83) 00 16 flash memory control register 0 (note ) flash memory control register 1 (note) flash command register (note) note: this re g ister is onl y exist in flash memor y version. (03b4 16 ) 01 0000 0 (03b5 16 ) 0 (03b6 16 ) 0 00 16 (90) (91) (92) 0
17 under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer software reset software reset writing 1 to bit 3 of the processor mode register 0 (address 0004 16 ) applies a (software reset) reset to the microcomputer. a software reset has almost the same effect as a hardware reset. the contents of internal ram are preserved. figure da-5 shows the processor mode register 0 and 1. figure da-5. processor mode register 0 and 1. processor mode register 0 (note) symbol address when reset pm0 0004 16 xxxx0000 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pm03 reserved bit software reset bit the device is reset when this bit is set to ?? the value of this bit is ??when read. note: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. processor mode register 1 (note) symbol address when reset pm1 0005 16 00xxxxx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 reserved bit must always be set to ? 0 note: set bit 1 of the protect register (address 000a 16 ) to ??when writing new values to this register. a a a a a a a a must always be set to 0 0 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. 0 0 0 0 0 reserved bit must always be set to 0 a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock generating circuit 18 figure wa-2. examples of sub clock clock generating circuit the clock generating circuit contains two oscillator circuits that supply the operating clock sources to the cpu and internal peripheral units. table wa-1. main clock and sub clock generating circuits example of oscillator circuit figure wa-1 shows some examples of the main clock circuit, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. figure wa-2 shows some examples of sub clock circuits, one using an oscillator connected to the circuit, and the other one using an externally derived clock for input. circuit constants in figures wa-1 and wa-2 vary with each oscillator used. use the values recommended by the manufacturer of your oscillator. figure wa-1. examples of main clock main clock generating circuit sub clock generating circuit use of clock ? cpus operating clock source ? cpus operating clock source ? internal peripheral units ? timer a/bs count clock operating clock source source usable oscillator ceramic or crystal oscillator crystal oscillator pins to connect oscillator x in , x out x cin , x cout oscillation stop/restart function available available oscillator status immediately after rese t oscillating stopped other externally derived clock can be input microcomputer (built-in feedback resistor) x in x out externally derived clock open vcc vss microcomputer (built-in feedback resistor) x in x out r d c in c out (note) note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x in and x out following the instruction. microcomputer (built-in feedback resistor) x cin x cout externally derived clock open vcc vss note: insert a damping resistor if required. the resistance will vary depending on the oscillator and the oscillation drive capacity setting. use the value recommended by the maker of the oscillator. when the oscillation drive capacity is set to low, check that oscillation is stable. also, if the oscillator manufacturer's data sheet specifies that a feedback resistor be added external to the chip, insert a feedback resistor between x cin and x cout following the instruction. microcomputer (built-in feedback resistor) x cin x cout (note) c cin c cout r cd
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock generating circuit 19 clock control figure wa-3 shows the block diagram of the clock generating circuit. figure wa-3. clock generating circuit sub clock cm04 f c32 cm0i : bit i at address 0006 16 cm1i : bit i at address 0007 16 wdci : bit i at address 000f 16 x cin cm10 ?? write signal 1/32 x cout q s r wait instruction x out main clock cm05 f c cm02 f 1 q s r interrupt request level judgment output reset software reset f c cm07=0 cm07=1 f ad aaa aaa divider a d 1/2 1/2 1/2 1/2 cm06=0 cm17,cm16=00 cm06=0 cm17,cm16=01 cm06=0 cm17,cm16=10 cm06=1 cm06=0 cm17,cm16=11 d a details of divider x in f 8 f 32 c b b 1/2 c bclk f 8sio2 f 1sio2
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock generating circuit 20 the following paragraphs describes the clocks generated by the clock generating circuit. (1) main clock the main clock is generated by the main clock oscillation circuit. after a reset, the clock is divided by 8 to the bclk. the clock can be stopped using the main clock stop bit (bit 5 at address 0006 16 ). stopping the clock, after switching the operating clock source of cpu to the sub-clock, reduces the power dissipation. after the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation circuit can be reduced using the x in -x out drive capacity select bit (bit 5 at address 0007 16 ). reducing the drive capacity of the main clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is re- tained. (2) sub-clock the sub-clock is generated by the sub-clock oscillation circuit. no sub-clock is generated after a reset. after oscillation is started using the port xc select bit (bit 4 at address 0006 16 ), the sub-clock can be selected as the bclk by using the system clock select bit (bit 7 at address 0006 16 ). however, be sure that the sub-clock oscillation has fully stabilized before switching. after the oscillation of the sub-clock oscillation circuit has stabilized, the drive capacity of the sub-clock oscillation circuit can be reduced using the x cin -x cout drive capacity select bit (bit 3 at address 0006 16 ). reducing the drive capacity of the sub-clock oscillation circuit reduces the power dissipation. this bit changes to 1 when shifting to stop mode and at a reset. (3) bclk the bclk is the clock that drives the cpu, and is fc or the clock is derived by dividing the main clock by 1, 2, 4, 8, or 16. the bclk is derived by dividing the main clock by 8 after a reset. the bclk signal can be output from bclk pin by the bclk output disable bit (bit 7 at address 0004 16 ) in the memory expan- sion and the microprocessor modes. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high- speed/medium-speed to stop mode and at reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. (4) peripheral function clock(f 1 , f 8 , f 32 , f ad , f 1sio2 , f 8sio2 ) the clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. the peripheral function clock is stopped by stopping the main clock or by setting the wait peripheral function clock stop bit (bit 2 at 0006 16 ) to 1 and then executing a wait instruction. (5) f c32 this clock is derived by dividing the sub-clock by 32. it is used for the timer a and timer b counts. (6) f c this clock has the same frequency as the sub-clock. it is used for the bclk and for the watchdog timer.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock generating circuit 21 figure wa-4 shows the system clock control registers 0 and 1. system clock control register 0 (note 1) symbol address when reset cm0 0006 16 48 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 0 0 : i/o port p9 7 /da 0 0 1 : f c output 1 0 : f 8 output 1 1 : f 32 output b1 b0 cm07 cm05 cm04 cm03 cm01 cm02 cm00 cm06 clock output function select bit (valid only in single-chip mode) wait peripheral function clock stop bit 0 : do not stop peripheral function clock in wait mode 1 : stop peripheral function clock in wait mode (note 8) x cin -x cout drive capacity select bit (note 2) 0 : low 1 : high port x c select bit 0 : i/o port 1 : x cin -x cout generation main clock (x in -x out ) stop bit (note 3, 4, 5) 0 : on 1 : off main clock division select bit 0 (note 7) 0 : cm16 and cm17 valid 1 : division by 8 mode system clock select bit (note 6) 0 : x in , x out 1 : x cin , x cout note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: changes to ??when shiffing to stop mode and at a reset. note 3: when entering power saving mode, main clock stops using this bit. when returning from stop mode and operating with x in , set this bit to ?? when main clock oscillation is operating by itself, set system clock select bit (cm07) to ??before setting this bit to ?? note 4: when inputting external clock, only clock oscillation buffer is stopped and clock input is acceptable. note 5: if this bit is set to ?? x out turns ?? the built-in feedback resistor remains being connected, so x in turns pulled up to x out (?? via the feedback resistor. note 6: set port xc select bit (cm04) to ??and stabilize the sub-clock oscillating before setting to this bit from ??to ? . do not write to both bits at the same time. and also, set the main clock stop bit (cm05) to ??and stabilize the main clock oscillating before setting this bit from ??to ?? note 7: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 8: f c32 is not included. system clock control register 1 (note 1) symbol address when reset cm1 0007 16 20 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 cm10 all clock stop control bit (note4) 0 : clock on 1 : all clocks off (stop mode) note 1: set bit 0 of the protect register (address 000a 16 ) to ??before writing to this register. note 2: this bit changes to ??when shifting from high-speed/medium-speed mode to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. note 3: can be selected when bit 6 of the system clock control register 0 (address 0006 16 ) is ?? if ?? division mode is fixed at 8. note 4: if this bit is set to ?? x out turns ?? and the built-in feedback resistor is cut off. x cin and x cout turn high- impedance state. cm15 x in -x out drive capacity select bit (note 2) 0 : low 1 : high w r w r cm16 cm17 reserved bit always set to ? reserved bit always set to ? main clock division select bit 1 (note 3) 0 0 : no division mode 0 1 : division by 2 mode 1 0 : division by 4 mode 1 1 : division by 16 mode b7 b6 0 0 reserved bit always set to ? reserved bit always set to ? 0 0 a aa a aa a aa a aa a a aa aa a aa a aa a aa a a aa aa a aa a aa a aa a aa a aa a aa figure wa-4. clock control registers 0 and 1
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock output 22 clock output the clock output function select bit (bit 0,1 at address 0006 16 ) allows you to choose the clock from f 8 , f 32 , or f c to be output from the p9 7 /da 0 /clk out /dim out pin. when the wait peripheral function clock stop bit (bit 2 at address 0006 16 ) is set to 1, the output of f 8 and f 32 stop by executing of wait instruction. stop mode writing 1 to the all-clock stop control bit (bit 0 at address 0007 16 ) stops all oscillation and the microcom- puter enters stop mode. in stop mode, the content of the internal ram is retained provided that v cc re- mains above 2v. because the oscillation of bclk, f 1 to f 32 , fc, f c32 , and f ad stops in stop mode, peripheral functions such as the fluorescent display function, serial i/o 2, a-d converter and watchdog timer do not function. however, timer a and timer b operate provided that the event counter mode is set to an external pulse, and uart0 and uart2 functions provided an external clock is selected. table wa-2 shows the status of the ports in stop mode. stop mode is cancelled by a hardware reset or an interrupt. if an interrupt is to be used to cancel stop mode, that interrupt must first have been enabled. if returning by an interrupt, that interrupt routine is executed. when shifting from high-speed/medium-speed mode to stop mode and at a reset, the main clock division select bit 0 (bit 6 at address 0006 16 ) is set to 1. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. table wa-2. port status during stop mode pin states port retains status before stop mode clk out when f c selected h when f 8 , f 32 selected retains status before stop mode wait mode when a wait instruction is executed, bclk stops and the microcomputer enters the wait mode. in this mode, oscillation continues but bclk and watchdog timer stop. writing 1 to the wait peripheral function clock stop bit and executing a wait instruction stops the clock being supplied to the internal peripheral functions, allowing power dissipation to be reduced. table wa-3 shows the status of the ports in wait mode. wait mode is cancelled by a hardware reset or an interrupt. if an interrupt is used to cancel wait mode, the microcomputer restarts from the interrupt routine using as bclk, the clock that had been selected when the wait instruction was executed. table wa-3. port status during wait mode pin states port retains status before wait mode clk out when f c selected does not stop when f 8 , f 32 selected does not stop when the wait peripheral function clock stop bit is 0. (note) when the wait peripheral function clock stop bit is 1, the status immediately prior to entering wait mode is maintained. note: attention that reducing the power dissipation is impossible.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer status transition of bclk 23 cm17 cm16 cm07 cm06 cm05 cm04 operating mode of bclk 0 1 0 0 0 invalid division by 2 mode 1 0 0 0 0 invalid division by 4 mode invalid invalid 0 1 0 invalid division by 8 mode 1 1 0 0 0 invalid division by 16 mode 0 0 0 0 0 invalid no-division mode invalid invalid 1 invalid 0 1 low-speed mode invalid invalid 1 invalid 1 1 low power dissipation mode table wa-4. operating modes dictated by settings of system clock control registers 0 and 1 status transition of bclk power dissipation can be reduced and low-voltage operation achieved by changing the count source for bclk. table wa-4 shows the operating modes corresponding to the settings of system clock control registers 0 and 1. when reset, the device starts in division by 8 mode. the main clock division select bit 0(bit 6 at address 0006 16 ) changes to 1 when shifting from high-speed/medium-speed to stop mode and at a reset. when shifting from low-speed/low power dissipation mode to stop mode, the value before stop mode is retained. the following shows the operational modes of bclk. (1) division by 2 mode the main clock is divided by 2 to obtain the bclk. (2) division by 4 mode the main clock is divided by 4 to obtain the bclk. (3) division by 8 mode the main clock is divided by 8 to obtain the bclk. when reset, the device starts operating from this mode. before the user can go from this mode to no division mode, division by 2 mode, or division by 4 mode, the main clock must be oscillating stably. when going to low-speed or lower power consumption mode, make sure the sub-clock is oscillating stably. (4) division by 16 mode the main clock is divided by 16 to obtain the bclk. (5) no-division mode the main clock is divided by 1 to obtain the bclk. (6) low-speed mode f c is used as the bclk. note that oscillation of both the main and sub-clocks must have stabilized before transferring from this mode to another or vice versa. at least 2 to 3 seconds are required after the sub- clock starts. therefore, the program must be written to wait until this clock has stabilized immediately after powering up and after stop mode is cancelled. (7) low power dissipation mode f c is the bclk and the main clock is stopped. note : before the count source for bclk can be changed from x in to x cin or vice versa, the clock to which the count source is going to be switched must be oscillating stably. allow a wait time in software for the oscillation to stabilize before switching over the clock.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer power control 24 power control the following is a description of the three available power control modes: modes power control is available in three modes. (a) normal operation mode ? high-speed mode divide-by-1 frequency of the main clock becomes the bclk. the cpu operates with the internal clock selected. each peripheral function operates according to its assigned clock. ? medium-speed mode divide-by-2, divide-by-4, divide-by-8, or divide-by-16 frequency of the main clock becomes the bclk. the cpu operates according to the internal clock selected. each peripheral function oper- ates according to its assigned clock. ? low-speed mode f c becomes the bclk. the cpu operates according to the fc clock. the fc clock is supplied by the secondary clock. each peripheral function operates according to its assigned clock. ? low power consumption mode the main clock operating in low-speed mode is stopped. the cpu operates according to the f c clock. the fc clock is supplied by the secondary clock. the only peripheral functions that operate are those with the sub-clock selected as the count source. (b) wait mode the cpu operation is stopped. the oscillators do not stop. (c) stop mode all oscillators stop. the cpu and all built-in peripheral functions stop. this mode, among the three modes listed here, is the most effective in decreasing power consumption. figure wa-5 is the state transition diagram of the above modes.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer power control 25 figure wa-5. state transition diagram of power control mode transition of stop mode, wait mode transition of normal mode reset medium-speed mode (divided-by-8 mode) interrupt cm10 = ? all oscillators stopped cpu operation stopped medium-speed mode (divided-by-8 mode) bclk : f(x in )/8 cm07 = ?? cm06 = ? low-speed mode high-speed mode main clock is oscillating sub clock is stopped main clock is oscillating sub clock is stopped main clock is stopped sub clock is oscillating main clock is oscillating sub clock is oscillating low power dissipation mode high-speed/medium- speed mode low-speed/low power dissipation mode normal mode stop mode stop mode stop mode all oscillators stopped all oscillators stopped wait mode wait mode wait mode cpu operation stopped cpu operation stopped interrupt wait instruction interrupt wait instruction interrupt wait instruction cm10 = ? interrupt interrupt cm10 = ? bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x in )/8 medium-speed mode (divided-by-8 mode) cm07 = ? cm06 = ? high-speed mode bclk : f(x in )/2 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-2 mode) bclk : f(x in )/16 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-16 mode) bclk : f(x in )/4 cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? medium-speed mode (divided-by-4 mode) bclk : f(x in ) cm07 = ?? cm06 = ? cm17 = ?? cm16 = ? bclk : f(x cin ) cm07 = ? bclk : f(x cin ) cm07 = ? main clock is oscillating sub clock is oscillating cm07 = ? (note 1, 3) cm07 = ??(note 1) cm06 = ? cm04 = ? cm07 = ? (note 2) cm07 = ??(note 1) cm06 = ??(note 3) cm04 = ? cm07 = ??(note 2) cm05 = ?? cm05 = ? cm05 = ? cm04 = ? cm04 = ? cm06 = ? (notes 1,3) cm06 = ? cm04 = ? cm04 = ? (notes 1, 3) note 1: switch clock after oscillation of main clock is sufficiently stable. note 2: switch clock after oscillation of sub clock is sufficiently stable. note 3: change cm06 after changing cm17 and cm16. note 4: transit in accordance with arrow. (refer to the following for the transition of normal mode.)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer protection 26 protection the protection function is provided so that the values in important registers cannot be changed in the event that the program runs out of control. figure wa-6 shows the protect register. the values in the processor mode register 0 (address 0004 16 ), processor mode register 1 (address 0005 16 ), system clock control reg- ister 0 (address 0006 16 ), and system clock control register 1 (address 0007 16 ) can only be changed when the respective bit in the protect register is set to 1. the system clock control registers 0 and 1 write-enable bit (bit 0 at address 000a 16 ) and processor mode register 0 and 1 write-enable bit (bit 1 at address 000a 16 ) do not automatically return to 0 after a value has been written to an address. the program must therefore be written to return these bits to 0. figure wa-6. protect register p r o t e c t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t p r c r0 0 0 a 1 6 x x x x x 0 0 0 2 b i t n a m e b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 0 : w r i t e - i n h i b i t e d 1 : w r i t e - e n a b l e d p r c 1 p r c 0 e n a b l e s w r i t i n g t o p r o c e s s o r m o d e r e g i s t e r s 0 a n d 1 ( a d d r e s s e s 0 0 0 4 1 6 a n d 0 0 0 5 1 6 ) f u n c t i o n 0 : w r i t e - i n h i b i t e d 1 : w r i t e - e n a b l e d e n a b l e s w r i t i n g t o s y s t e m c l o c k c o n t r o l r e g i s t e r s 0 a n d 1 ( a d d r e s s e s 0 0 0 6 1 6 a n d 0 0 0 7 1 6 ) w r n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e .
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 27 ? maskable interrupt : an interrupt which can be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority can be changed by priority level. ? non-maskable interrupt : an interrupt which cannot be enabled (disabled) by the interrupt enable flag (i flag) or whose interrupt priority cannot be changed by priority level. figure dd-1. classification of interrupts interrupt ? ? ? y ? ? ? t software hardware ? y ? t special peripheral i/o (note) ? y ? t undefined instruction (und instruction) overflow (into instruction) brk instruction int instruction ? ? y ? ? t reset ________ dbc watchdog timer single step address matched note: peripheral i/o interrupts are generated by the peripheral functions built into the microcomputer system. overview of interrupt type of interrupts figure dd-1 lists the types of interrupts.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 28 software interrupts a software interrupt occurs when executing certain instructions. software interrupts are non-maskable interrupts. ? undefined instruction interrupt an undefined instruction interrupt occurs when executing the und instruction. ? overflow interrupt an overflow interrupt occurs when executing the into instruction with the overflow flag (o flag) set to 1. the following are instructions whose o flag changes by arithmetic: abs, adc, adcf, add, cmp, div, divu, divx, neg, rmpa, sbb, sha, sub ? brk interrupt a brk interrupt occurs when executing the brk instruction. ? int interrupt an int interrupt occurs when specifying one of software interrupt numbers 0 through 63 and execut- ing the int instruction. software interrupt numbers 0 through 31 are assigned to peripheral i/o inter- rupts, so executing the int instruction allows executing the same interrupt routine that a peripheral i/ o interrupt does. the stack pointer (sp) used for the int interrupt is dependent on which software interrupt number is involved. so far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assignment flag (u flag) when it accepts an interrupt request. if change the u flag to 0 and select the interrupt stack pointer (isp), and then execute an interrupt sequence. when returning from the interrupt routine, the u flag is returned to the state it was before the acceptance of interrupt re- quest. so far as software numbers 32 through 63 are concerned, the stack pointer does not make a shift.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 29 hardware interrupts hardware interrupts are classified into two types special interrupts and peripheral i/o interrupts. (1) special interrupts special interrupts are non-maskable interrupts. ? reset ____________ reset occurs if an l is input to the reset pin. ________ ? dbc interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. ? watchdog timer interrupt generated by the watchdog timer. ? single-step interrupt this interrupt is exclusively for the debugger, do not use it in other circumstances. with the debug flag (d flag) set to 1, a single-step interrupt occurs after one instruction is executed. ? address match interrupt an address match interrupt occurs immediately before the instruction held in the address indicated by the address match interrupt register is executed with the address match interrupt enable bit set to 1. if an address other than the first address of the instruction in the address match interrupt register is set, no address match interrupt occurs. (2) peripheral i/o interrupts a peripheral i/o interrupt is generated by one of built-in peripheral functions. built-in peripheral func- tions are dependent on classes of products, so the interrupt factors too are dependent on classes of products. the interrupt vector table is the same as the one for software interrupt numbers 0 through 31 the int instruction uses. peripheral i/o interrupts are maskable interrupts. ? dma0 interrupt, dma1 interrupt these are interrupts that dma generates. ? a-d conversion interrupt this is an interrupt that the a-d converter generates. ? uart0 and uart1 transmission interrupt these are interrupts that the serial i/o transmission generates. ? uart0 and uart1 reception interrupt these are interrupts that the serial i/o reception generates. ? si/o automatic transfer interrupt this is an interrupt that the si/o automatic transfer generates. ? timer a0 interrupt through timer a4 interrupt these are interrupts that timer a generates ? timer b0 interrupt through timer b2 interrupt these are interrupts that timer b generates. ________ ________ ? int0 interrupt through int5 interrupt ______ ______ an int interrupt occurs if either a rising edge or a falling edge is input to the int pin.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 30 interrupt source vector table addresses remarks address (l) to address (h) undefined instruction fffdc 16 to fffdf 16 interrupt on und instruction overflow fffe0 16 to fffe3 16 interrupt on into instruction brk instruction fffe4 16 to fffe7 16 if the vector contains ff 16 , program execution starts from the address shown by the vector in the variable vector table address match fffe8 16 to fffeb 16 there is an address-matching interrupt enable bit single step (note) fffec 16 to fffef 16 do not use watchdog timer ffff0 16 to ffff3 16 ________ dbc (note) ffff4 16 to ffff7 16 do not use - ffff8 16 to ffffb 16 - reset ffffc 16 to fffff 16 note: interrupts used for debugging purposes only. figure dd-2. format for specifying interrupt vector addresses m i d a d d r e s s l o w a d d r e s s 0 0 0 0h i g h a d d r e s s 0 0 0 0 0 0 0 0 v e c t o r a d d r e s s + 0 v e c t o r a d d r e s s + 1 v e c t o r a d d r e s s + 2 v e c t o r a d d r e s s + 3 l s b m s b interrupts and interrupt vector tables if an interrupt request is accepted, a program branches to the interrupt routine set in the interrupt vector table. set the first address of the interrupt routine in each vector table. figure dd-2 shows the format for specifying the address. two types of interrupt vector tables are available fixed vector table in which addresses are fixed and variable vector table in which addresses can be varied by the setting. ? fixed vector tables the fixed vector table is a table in which addresses are fixed. the vector tables are located in an area extending from fffdc 16 to fffff 16 . one vector table comprises four bytes. set the first address of interrupt routine in each vector table. table dd-1 shows the interrupts assigned to the fixed vector tables and addresses of vector tables. table dd-1. interrupts assigned to the fixed vector tables and addresses of vector tables
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 31 table dd-2. interrupts assigned to the variable vector tables and addresses of vector tables software interrupt number interrupt source vector table address address (l) to address (h) remarks cannot be masked i flag +0 to +3 (note) brk instruction software interrupt number 0 +44 to +47 (note) software interrupt number 11 +48 to +51 (note) software interrupt number 12 +56 to +59 (note) software interrupt number 14 +68 to +71 (note) software interrupt number 17 +72 to +75 (note) software interrupt number 18 +76 to +79 (note) software interrupt number 19 +80 to +83 (note) software interrupt number 20 +84 to +87 (note) software interrupt number 21 +88 to +91 (note) software interrupt number 22 +92 to +95 (note) software interrupt number 23 +96 to +99 (note) software interrupt number 24 +100 to +103 (note) software interrupt number 25 +104 to +107 (note) software interrupt number 26 +108 to +111 (note) software interrupt number 27 +112 to +115 (note) software interrupt number 28 +116 to +119 (note) software interrupt number 29 +120 to +123 (note) software interrupt number 30 +124 to +127 (note) software interrupt number 31 +128 to +131 (note) software interrupt number 32 +252 to +255 (note) software interrupt number 63 to note : address relative to address in interrupt table register (intb). cannot be masked i flag to a-d uart0 transmit uart0 receive uart1 transmit uart1 receive timer a0 timer a1 timer a2 timer a3 timer b0 timer b1 int0 int1 software interrupt +28 to +31 (note) int3 software interrupt number 7 +32 to +35 (note) int4 software interrupt number 8 +36 to +39 (note) int5 software interrupt number 9 dma0 dma1 +60 to +63 (note) software interrupt number 15 si/o automatic transfer +64 to +67 (note) software interrupt number 16 fld timer a4 timer b2 int2 ? variable vector tables the addresses in the variable vector table can be modified, according to the users settings. indicate the first address using the interrupt table register (intb). the 256-byte area subsequent to the ad- dress the intb indicates becomes the area for the variable vector tables. one vector table comprises four bytes. set the first address of the interrupt routine in each vector table. table dd-2 shows the interrupts assigned to the variable vector tables and addresses of vector tables.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 32 interrupt control descriptions are given here regarding how to enable or disable maskable interrupts and how to set the priority to be accepted. what is described here does not apply to non-maskable interrupts. enable or disable a maskable interrupt using the interrupt enable flag (i flag), interrupt priority level selec- tion bit, or processor interrupt priority level (ipl). whether an interrupt request is present or absent is indicated by the interrupt request bit. the interrupt request bit and the interrupt priority level selection bit are located in the interrupt control register of each interrupt. also, the interrupt enable flag (i flag) and the ipl are located in the flag register (flg). figure dd-3 shows the memory map of the interrupt control registers.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 33 figure dd-3. interrupt control registers symbol address when reset intiic(i=0 to 5) 005d 16 to 005f 16 xx00x000 2 0047 16 to 0049 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a a aa aa ilvl0 ir pol interrupt priority level select bit interrupt request bit polarity select bit reserved bit 0: interrupt not requested 1: interrupt requested 0 : selects falling edge 1 : selects rising edge always set to 0 ilvl1 ilvl2 note1 : this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. (note1) interrupt control register(note2) b7 b6 b5 b4 b3 b2 b1 b0 a aa aa a bit name function bit symbol w r symbol address when reset dmiic(i=0, 1) 004b 16 to 004c 16 xxxxx000 2 adic 004e 16 xxxxx000 2 asioic 004f 16 xxxxx000 2 fldic 0050 16 xxxxx000 2 sitic(i=0, 1) 0051 16 , 0053 16 xxxxx000 2 siric(i=0, 1) 0052 16 , 0054 16 xxxxx000 2 taiic(i=0 to 4) 0055 16 to 0059 16 xxxxx000 2 tbiic(i=0 to 2) 005a 16 to 005c 16 xxxxx000 2 ilvl0 ir interrupt priority level select bit interrupt request bit 0 : interrupt not requested 1 : interrupt requested ilvl1 ilvl2 nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate. (note1) note 1: this bit can only be accessed for reset (= 0), but cannot be accessed for set (= 1). note 2: to rewrite the interrupt control register, do so at a point that dose not generate the interrupt request for that register. for details, see the precautions for interrupts. 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 0 0 : level 0 (interrupt disabled) 0 0 1 : level 1 0 1 0 : level 2 0 1 1 : level 3 1 0 0 : level 4 1 0 1 : level 5 1 1 0 : level 6 1 1 1 : level 7 b2 b1 b0 0 a a a a a a a a a a a a a a a a a a a a a a a a nothing is assigned. in an attempt to write to these bits, write 0. the value, if read, turns out to be indeterminate.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 34 interrupt enable flag (i flag) the interrupt enable flag (i flag) controls the enabling and disabling of maskable interrupts. setting this flag to 1 enables all maskable interrupts; setting it to 0 disables all maskable interrupts. this flag is set to 0 after reset. interrupt request bit the interrupt request bit is set to "1" by hardware when an interrupt is requested. after the interrupt is accepted and jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. the interrupt request bit can also be set to "0" by software. (do not set this bit to "1"). table dd-4. interrupt levels enabled according to the contents of the ipl table dd-3. settings of interrupt priority levels interrupt priority level select bit interrupt priority level priority order 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 level 0 (interrupt disabled) level 1 level 2 level 3 level 4 level 5 level 6 level 7 low high b2 b1 b0 enabled interrupt priority levels 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 interrupt levels 1 and above are enabled interrupt levels 2 and above are enabled interrupt levels 3 and above are enabled interrupt levels 4 and above are enabled interrupt levels 5 and above are enabled interrupt levels 6 and above are enabled interrupt levels 7 and above are enabled all maskable interrupts are disabled ipl 2 ipl 1 ipl 0 ipl interrupt priority level select bit and processor interrupt priority level (ipl) set the interrupt priority level using the interrupt priority level select bit, which is one of the component bits of the interrupt control register. when an interrupt request occurs, the interrupt priority level is compared with the ipl. the interrupt is enabled only when the priority level of the interrupt is higher than the ipl. therefore, setting the interrupt priority level to 0 disables the interrupt. table dd-3 shows the settings of interrupt priority levels and table dd-4 shows the interrupt levels enabled, according to the consist of the ipl. the following are conditions under which an interrupt is accepted: interrupt enable flag (i flag) = 1 interrupt request bit = 1 interrupt priority level > ipl the interrupt enable flag (i flag), the interrupt request bit, the interrupt priority select bit, and the ipl are independent, and they are not affected by one another.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 35 example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. rewrite the interrupt control register to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 36 interrupt sequence an interrupt sequence what are performed over a period from the instant an interrupt is accepted to the instant the interrupt routine is executed is described here. if an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the instruction is completed, and transfers control to the interrupt sequence from the next cycle. if an interrupt occurs during execution of either the smovb, smovf, sstr or rmpa instruction, the processor temporarily suspends the instruction being executed, and transfers control to the interrupt sequence. in the interrupt sequence, the processor carries out the following in sequence given: (1) cpu gets the interrupt information (the interrupt number and interrupt request level) by reading ad- dress 00000 16 . (2) saves the content of the flag register (flg) as it was immediately before the start of interrupt sequence in the temporary register (note) within the cpu. (3) sets the interrupt enable flag (i flag), the debug flag (d flag), and the stack pointer select flag (u flag) to 0 (the u flag, however does not change if the int instruction, in software interrupt numbers 32 through 63, is executed) (4) saves the content of the temporary register (note) within the cpu in the stack area. (5) saves the content of the program counter (pc) in the stack area. (6) sets the interrupt priority level of the accepted instruction in the ipl. after the interrupt sequence is completed, the processor resumes executing instructions from the first address of the interrupt routine. note: this register cannot be utilized by the user. interrupt response time 'interrupt response time' is the period between the instant an interrupt occurs and the instant the first instruction within the interrupt routine has been executed. this time comprises the period from the occurrence of an interrupt to the completion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b). figure dd-4 shows the interrupt response time. instruction interrupt sequence instruction in interrupt routine time interrupt response time (a) (b) interrupt request acknowledged interrupt request generated (a) time from interrupt request is generated to when the instruction then under execution is completed. (b) time in which the instruction sequence is executed. figure dd-4. interrupt response time
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 37 interrupt sources without priority levels 7 value set in the ipl watchdog timer other not changed 0 variation of ipl when interrupt request is accepted if an interrupt request is accepted, the interrupt priority level of the accepted interrupt is set in the ipl. if an interrupt request, that does not have an interrupt priority level, is accepted, one of the values shown in table dd-6 is set in the ipl. table dd-6. relationship between interrupts without interrupt priority levels and ipl stack pointer (sp) value interrupt vector address 16-bit bust 8-bit bus even even odd (note 2) odd (note 2) even odd even odd 18 cycles (note 1) 19 cycles (note 1) 19 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) 20 cycles (note 1) table dd-5. time required for executing the interrupt sequence reset indeterminate 123456789 1011 12 13 14 15 16 17 18 the indeterminate segment is dependent on the queue buffer. if the queue buffer is ready to take an instruction, a read cycle occurs. indeterminate sp-2 contents sp-4 contents vec contents vec+2 contents interrupt information address 0000 indeterminate sp-2 sp-4 vec vec+2 pc bclk address bus data bus w r time (a) is dependent on the instruction under execution. thirty cycles is the maximum required for the divx instruction. time (b) is as shown in table dd-5. ________ note 1: add 2 cycles in the case of a dbc interrupt; add 1 cycle in the case either of an address coincidence interrupt or of a single-step interrupt. note 2: locate an interrupt vector address in an even address, if possible. figure dd-5. time required for executing the interrupt sequence
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 38 saving registers in the interrupt sequence, only the contents of the flag register (flg) and that of the program counter (pc) are saved in the stack area. first, the processor saves the four higher-order bits of the program counter, and 4 upper-order bits and 8 lower-order bits of the flg register, 16 bits in total, in the stack area, then saves 16 lower-order bits of the program counter. figure dd-6 shows the state of the stack as it was before the acceptance of the interrupt request, and the state the stack after the acceptance of the interrupt request. save other necessary registers at the beginning of the interrupt routine using software. using the pushm instruction alone can save all the registers except the stack pointer (sp). address content of previous stack stack area [sp] stack pointer value before interrupt occurs m m ?1 m ?2 m ?3 m ?4 stack status before interrupt request is acknowledged stack status after interrupt request is acknowledged content of previous stack m + 1 msb lsb m m ?1 m ?2 m ?3 m ?4 address flag register (flg l ) content of previous stack stack area flag register (flg h ) program counter (pc h ) [sp] new stack pointer value content of previous stack m + 1 msb lsb program counter (pc l ) program counter (pc m ) figure dd-6. state of stack before and after acceptance of interrupt request
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 39 figure dd-7. operation of saving registers (2) stack pointer (sp) contains odd number [sp] (odd) [sp] ?1 (even) [sp] ?2(odd) [sp] ?3 (even) [sp] ?4(odd) [sp] ?5 (even) address sequence in which order registers are saved (2) (1) finished saving registers in four operations. (3) (4) (1) stack pointer (sp) contains even number [sp] (even) [sp] ?1(odd) [sp] ?2 (even) [sp] ?3(odd) [sp] ?4 (even) [sp] ?5 (odd) note: [sp] denotes the initial value of the stack pointer (sp) when interrupt request is acknowledged. after registers are saved, the sp content is [sp] minus 4. address program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) sequence in which order registers are saved (2) saved simultaneously, all 16 bits (1) saved simultaneously, all 16 bits finished saving registers in two operations. program counter (pc m ) stack area flag register (flg l ) program counter (pc l ) saved simultaneously, all 8 bits flag register (flg h ) program counter (pc h ) flag register (flg h ) program counter (pc h ) the operation of saving registers carried out in the interrupt sequence is dependent on whether the content of the stack pointer, at the time of acceptance of an interrupt request, is even or odd- if the content of the stack pointer (note) is even, the content of the flag register (flg) and the content of the program counter (pc) are saved, 16 bits at a time. if odd, their contents are saved in two steps, 8 bits at a time. figure dd-7 shows the operation of the saving registers. note: stack pointer indicated by u flag.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 40 interrupt priority if there are two or more interrupt requests occurring at a point in time within a single sampling (checking whether interrupt requests are made), the interrupt assigned a higher priority is accepted. assign an arbitrary priority to maskable interrupts (peripheral i/o interrupts) using the interrupt priority level select bit. if the same interrupt priority level is assigned, however, the interrupt assigned a higher hardware priority is accepted. priorities of the special interrupts, such as reset (dealt with as an interrupt assigned the highest priority), watchdog timer interrupt, etc. are regulated by hardware. figure dd-8 shows the priorities of hardware interrupts. software interrupts are not affected by the interrupt priority. if an instruction is executed, control branches invariably to the interrupt routine. returning from an interrupt routine executing the reit instruction at the end of an interrupt routine returns the contents of the flag register (flg) as it was immediately before the start of interrupt sequence and the contents of the program counter (pc), both of which have been saved in the stack area. then control returns to the program that was being executed before the acceptance of the interrupt request, so that the suspended process resumes. return the other registers saved by software within the interrupt routine using the popm or similar instruc- tion before executing the reit instruction. interrupt resolution circuit when two or more interrupts are generated simultaneously, this circuit selects the interrupt with the highest priority level. figure dd-9 shows the circuit that judges the interrupt priority level. figure dd-8. hardware interrupts priorities ________ reset > dbc > watchdog timer > peripheral i/o > single step > address match
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer interrupt 41 figure dd-9. maskable interrupts priorities timer b0 timer a3 int2 timer b1 int3 uart1 reception uart0 reception fld timer a0 uart1 transmission uart0 transmission si/o2 automatic transfer processor interrupt priority level (ipl) interrupt enable flag (i flag) timer b2 int0 watchdog timer reset dbc interrupt request accepted level 0 (initial value) priority level of each interrupt high low priority of peripheral i/o interrupts (if priority levels are same) address match int1 timer a1 int4 timer a4 timer a2 int5 a-d conversion dma1 dma0 interrupt request level judgment output
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer address match interrupt 42 address match interrupt an address match interrupt is generated when the address match interrupt address register contents match the program counter value. two address match interrupts can be set, each of which can be enabled and disabled by an address match interrupt enable bit. address match interrupts are not affected by the inter- rupt enable flag (i flag) and processor interrupt priority level (ipl). the value of the program counter (pc) for an address match interrupt varies depending on the instruction being executed. figure dd-12 shows the address match interrupt-related registers. b i t n a m e b i t s y m b o l s y m b o la d d r e s s w h e n r e s e t a i e r0 0 0 9 1 6 x x x x x x 0 0 2 a d d r e s s m a t c h i n t e r r u p t e n a b l e r e g i s t e r f u n c t i o n w r a d d r e s s m a t c h i n t e r r u p t 0 e n a b l e b i t 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d a i e r 0 a d d r e s s m a t c h i n t e r r u p t 1 e n a b l e b i t a i e r 1 s y m b o la d d r e s s w h e n r e s e t r m a d 00 0 1 2 1 6 t o 0 0 1 0 1 6 x 0 0 0 0 0 1 6 r m a d 10 0 1 6 1 6 t o 0 0 1 4 1 6 x 0 0 0 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 w r a d d r e s s s e t t i n g r e g i s t e r f o r a d d r e s s m a t c h i n t e r r u p t f u n c t i o nv a l u e s t h a t c a n b e s e t a d d r e s s m a t c h i n t e r r u p t r e g i s t e r i ( i = 0 , 1 ) 0 0 0 0 0 1 6 t o f f f f f 1 6 0 : i n t e r r u p t d i s a b l e d 1 : i n t e r r u p t e n a b l e d b 0b 7b 0 b 3 ( b 1 9 )( b 1 6 ) b 7b 0 ( b 1 5 )( b 8 ) b 7 ( b 2 3 ) n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . figure dd-12. address match interrupt-related registers
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer precautions for interrupts 43 ______ figure dd-13. switching condition of int interrupt request set the polarity select bit clear the interrupt request bit to ? set the interrupt priority level to level 1 to 7 (enable the accepting of inti interrupt request) set the interrupt priority level to level 0 (disable inti interrupt) clear the interrupt enable flag to ? (disable interrupt) set the interrupt enable flag to ? (enable interrupt) precautions for interrupts (1) reading address 00000 16 ? when maskable interrupt is occurred, cpu read the interrupt information (the interrupt number and interrupt request level) in the interrupt sequence. the interrupt request bit of the certain interrupt written in address 00000 16 will then be set to 0. reading address 00000 16 by software sets enabled highest priority interrupt source request bit to 0. though the interrupt is generated, the interrupt routine may not be executed. do not read address 00000 16 by software. (2) setting the stack pointer ? the value of the stack pointer immediately after reset is initialized to 0000 16 . accepting an interrupt before setting a value in the stack pointer may become a factor of runaway. be sure to set a value in the stack pointer before accepting an interrupt. (3) external interrupt ________ ? either an l level or an h level of at least 250 ns width is necessary for the signal input to pins int 0 ________ through int 5 regardless of the cpu operation clock. ________ ________ ? when the polarity of the int 0 through int 5 pins is changed, the interrupt request bit is sometimes set to 1. after changing the polarity, set the interrupt request bit to 0. figure dd-13 shows the procedure ______ for changing the int interrupt generate factor.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer precautions for interrupts 44 example 1: int_switch1: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. nop ; nop fset i ; enable interrupts. example 2: int_switch2: fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. mov.w mem, r0 ; dummy read. fset i ; enable interrupts. example 3: int_switch3: pushc flg ; fclr i ; disable interrupts. and.b #00h, 0055h ; clear ta0ic int. priority level and int. request bit. popc flg ; enable interrupts. the reason why two nop instructions or dummy read are inserted before fset i in examples 1 and 2 is to prevent the interrupt enable flag i from being set before the interrupt control register is rewritten due to effects of the instruction queue. (5) rewrite the interrupt control register ? to rewrite the interrupt control register, do so at a point that does not generate the interrupt request for that register. if there is possibility of the interrupt request occur, rewrite the interrupt control register after the interrupt is disabled. the program examples are described as follow: ? when a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request bit is not set sometimes even if the interrupt request for that register has been gener- ated. this will depend on the instruction. if this creates problems, use the below instructions to change the register. instructions : and, or, bclr, bset
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer watchdog timer 45 figure fa-1. block diagram of watchdog timer bclk write to the watchdog timer start register (address 000e 16 ) reset watchdog timer interrupt request watchdog timer set to ?fff 16 1/128 1/16 ?m07 = 0 ?dc7 = 1 ?m07 = 0 ?dc7 = 0 ?m07 = 1 1/2 prescaler watchdog timer the watchdog timer has the function of detecting when the program is out of control. the watchdog timer is a 15-bit counter which down-counts the clock derived by dividing the bclk using the prescaler. a watchdog timer interrupt is generated when an underflow occurs in the watchdog timer. when x in is selected for the bclk , bit 7 of the watchdog timer control register (address 000f 16 ) selects the prescaler division ratio (by 16 or by 128). when x cin is selected as the bclk, the prescaler is set for division by 2 regardless of bit 7 of the watchdog timer control register (address 000f 16 ). thus the watchdog timer's period can be calcu- lated as given below. the watchdog timer's period is, however, subject to an error due to the prescaler. for example, suppose that bclk runs at 10 mhz and that 16 has been chosen for the dividing ratio of the prescaler, then the watchdog timer's period becomes approximately 52.4 ms. the watchdog timer is initialized by writing to the watchdog timer start register (address 000e 16 ) and when a watchdog timer interrupt request is generated. the prescaler is initialized only when the microcomputer is reset. after a reset is cancelled, the watchdog timer and prescaler are both stopped. the count is started by writing to the watchdog timer start register (address 000e 16 ). figure fa-1 shows the block diagram of the watchdog timer. figure fa-2 shows the watchdog timer-related registers. with x in chosen for bclk watchdog timer period = prescaler dividing ratio (16 or 128) x watchdog timer count (32768) bclk with x cin chosen for bclk watchdog timer period = prescaler dividing ratio (2) x watchdog timer count (32768) bclk
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer watchdog timer 46 figure fa-2. watchdog timer control and start registers watchdog timer control register symbol address when reset wdc 000f 16 000xxxxx 2 function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 high-order bit of watchdog timer wdc7 bit name prescaler select bit 0 : divided by 16 1 : divided by 128 watchdog timer start register symbol address when reset wdts 000e 16 indeterminate w r b7 b0 function the watchdog timer is initialized and starts counting after a write instruction to this register. the watchdog timer value is always initialized to ?fff 16 regardless of whatever value is written. reserved bit reserved bit must always be set to ? must always be set to ? 0 0 aa aa a aa aa a a aa aa a a a
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer dmac 47 figure ec-1. block diagram of dmac dmac this microcomputer has two dmac (direct memory access controller) channels that allow data to be sent to memory without using the cpu. dmac shares the same data bus with the cpu. the dmac is given a higher right of using the bus than the cpu, which leads to working the cycle stealing method. on this account, the operation from the occurrence of dma transfer request signal to the completion of 1-word (16- bit) or 1-byte (8-bit) data transfer can be performed at high speed. figure ec-1 shows the block diagram of the dmac. table ec-1 shows the dmac specifications. figure ec-2 to figure ec-3 show the registers used by the dmac. either a write signal to the software dma request bit or an interrupt request signal is used as a dma transfer request signal. but the dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. the dma transfer doesn't affect any interrupts either. if the dmac is active (the dma enable bit is set to 1), data transfer starts every time a dma transfer request signal occurs. if the cycle of the occurrences of dma transfer request signals is higher than the dma transfer cycle, there can be instances in which the number of transfer requests doesn't agree with the number of transfers. for details, see the description of the dma request bit. aa aa aa aa aa aa aa aa aa aa a a aa aa aa aa aa aa aa aa aa aa aa aaaaaa aaaaaa data bus low-order bits dma latch high-order bits dma latch low-order bits dma0 source pointer sar0(20) dma0 destination pointer dar0 (20) dma0 forward address pointer (20) (note) aaaaaaa data bus high-order bits a a a a a a aaaaaaaaaaaaaaaaaaaaaaaa aaaaaaa address bus a a a a dma1 destination pointer dar1 (20) dma1 source pointer sar1 (20) dma1 forward address pointer (20) (note) aa aa aa aa dma0 transfer counter reload register tcr0 (16) dma0 transfer counter tcr0 (16) dma1 transfer counter reload register tcr1 (16) dma1 transfer counter tcr1 (16) aa aa (addresses 0029 16 , 0028 16 ) (addresses 0039 16 , 0038 16 ) (addresses 0022 16 to 0020 16 ) (addresses 0026 16 to 0024 16 ) (addresses 0032 16 to 0030 16 ) (addresses 0036 16 to 0034 16 ) note: pointer is incremented b y a dma re q uest. aa aa aa aa aa aa aa a a a a a a a a a a aa aa aa a a a a a a a a
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer dmac 48 item specification no. of channels 2 (cycle steal method) transfer memory space ? from any address in the 1m bytes space to a fixed address ? from a fixed address to any address in the 1m bytes space ? from a fixed address to a fixed address (note that dma-related registers [0020 16 to 003f 16 ] cannot be accessed) maximum no. of bytes transferred 128k bytes (with 16-bit transfers) or 64k bytes (with 8-bit transfers) dma request factors (note) ________ ________ ________ ________ falling edge of int0 or int1 (int0 can be selected by dma0, int1 by dma1) timer a0 to timer a4 interrupt requests timer b0 to timer b2 interrupt requests uart0 transmission and reception interrupt requests uart1 transmission and reception interrupt requests a-d conversion interrupt requests software triggers channel priority dma0 takes precedence if dma0 and dma1 requests are generated simultaneously transfer unit 8 bits or 16 bits transfer address direction forward or fixed (forward direction cannot be specified for both source and destination simultaneously) transfer mode ? single transfer mode after the transfer counter underflows, the dma enable bit turns to 0, and the dmac turns inactive ? repeat transfer mode after the transfer counter underflows, the value of the transfer counter reload register is reloaded to the transfer counter. the dmac remains active unless a 0 is written to the dma enable bit. dma interrupt request generation timing when an underflow occurs in the transfer counter active when the dma enable bit is set to 1, the dmac is active. when the dmac is active, data transfer starts every time a dma transfer request signal occurs. inactive ? when the dma enable bit is set to 0, the dmac is inactive. ? after the transfer counter underflows in single transfer mode at the time of starting data transfer immediately after turning the dmac active, re the value of one of source pointer and destination pointer - the one specified for the forward direction - is reloaded to the forward direction address pointer,and the value of the transfer counter reload register is reloaded to the transfer counter. writing to register registers specified for forward direction transfer are always write enabled. registers specified for fixed address transfer are write-enabled when the dma enable bit is 0. reading the register can be read at any time. however, when the dma enable bit is 1, reading the register set up as the forward register is the same as reading the value of the forward address pointer. table ec-1. dmac specifications note: dma transfer is not effective to any interrupt. dma transfer is affected neither by the interrupt enable flag (i flag) nor by the interrupt priority level. forward address pointer and load timing for transfer counter
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer dmac 49 figure ec-2. dmac-related registers (1) dmai request cause select register symbol address when reset dmisl(i=0,1) 03b8 16 ,03ba 16 00 16 bit name function r bit symbol w b7 b6 b5 b4 b3 b2 b1 b0 dma request cause select bit dsel0 dsel1 dsel2 dsel3 software dma request bit if software trigger is selected, a dma request is generated by setting this bit to ?? (when read, the value of this bit is always ?? dsr dmai control register symbol address when reset dmicon(i=0,1) 002c 16 , 003c 16 00000x00 2 bit name function bit symbol r w b7 b6 b5 b4 b3 b2 b1 b0 transfer unit bit select bit 0 : 16 bits 1 : 8 bits dmbit dmasl dmas dmae repeat transfer mode select bit 0 : single transfer 1 : repeat transfer dma request bit (note 1) 0 : dma not requested 1 : dma requested 0 : disabled 1 : enabled 0 : fixed 1 : forward dma enable bit source address direction select bit (note 3) destination address direction select bit (note 3) 0 : fixed 1 : forward dsd dad note 1: dma request can be cleared by resetting the bit. note 2: this bit can only be set to ?? note 3: source address direction select bit and destination address direction select bit cannot be set to ??simultaneously. b3 b2 b1 b0 0 0 0 0 : falling edge of int0 / int1 pin (note) 0 0 0 1 : software trigger 0 0 1 0 : timer a0 0 0 1 1 : timer a1 0 1 0 0 : timer a2 0 1 0 1 : timer a3 0 1 1 0 : timer a4 0 1 1 1 : timer b0 1 0 0 0 : timer b1 1 0 0 1 : timer b2 1 0 1 0 : uart0 transmit 1 0 1 1 : uart0 receive 1 1 0 0 : uart1 transmit 1 1 0 1 : uart1 receive 1 1 1 0 : a-d conversion 1 1 1 1 : inhibited note: address 03b8 16 is for int0; address 03ba 16 is for int1. (note 2) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ??
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer dmac 50 figure ec-3. dmac-related registers (2) b7 b0 b7 b0 (b8) (b15) function rw ?transfer counter set a value one less than the transfer count symbol address when reset tcr0 0029 16 , 0028 16 indeterminate tcr1 0039 16 , 0038 16 indeterminate dmai transfer counter (i = 0, 1) transfer count specification 0000 16 to ffff 16 b7 (b23) b3 b0 b7 b0 b7 b0 (b8) (b16)(b15) (b19) function rw ?source pointer stores the source address symbol address when reset sar0 0022 16 to 0020 16 indeterminate sar1 0032 16 to 0030 16 indeterminate dmai source pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? symbol address when reset dar0 0026 16 to 0024 16 indeterminate dar1 0036 16 to 0034 16 indeterminate b3 b0 b7 b0 b7 b0 (b8) (b15) (b16) (b19) function rw ?destination pointer stores the destination address dmai destination pointer (i = 0, 1) transfer count specification 00000 16 to fffff 16 b7 (b23) nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? a a aa aa a aa a aa
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer dmac 51 figure ec-4. example of transfer cycles for a source read (the state of internal bus) bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle (1) 8-bit transfers 16-bit transfers and the source address is even. bclk address bus rd signal wr signal data bus cpu use cpu use cpu use cpu use source source destination destination dummy cycle dummy cycle source + 1 source + 1 (2) 16-bit transfers and the source address is odd note: the same timin g chan g es occur with the respective conditions at the destination as at the source. (1) transfer cycle the transfer cycle consists of the bus cycle in which data is read from memory or from the sfr area (source read) and the bus cycle in which the data is written to memory or to the sfr area (destination write). the number of read and write bus cycles depends on the source and destination addresses. (a) effect of source and destination addresses when 16-bit data is transferred on a 16-bit data bus, and the source and destination both start at odd addresses, there are one more source read cycle and destination write cycle than when the source and destination both start at even addresses. figure ec-4 shows the example of the transfer cycles (a state of internal bus) for a source read. for convenience, the destination write cycle is shown as one cycle and the source read cycles for the differ- ent conditions are shown. in reality, the destination write cycle is subject to the same conditions as the source read cycle, with the transfer cycle changing accordingly. when calculating the transfer cycle, remember to apply the respective conditions to both the destination write cycle and the source read cycle.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer dmac 52 (2) dmac transfer any combination of even or odd transfer read and write addresses is possible. table ec-2 shows the number of dmac transfer cycles. the number of dmac transfer cycles can be calculated as follows: no. of transfer cycles per transfer unit = no. of read cycles x j + no. of write cycles x k table ec-2. no. of dmac transfer cycles singelchip mode transfer unit access address no. of no. of read cycles write cycles 8-bit transfers even 1 1 (dmbit="1") odd 1 1 16-bit transfers even 1 1 (dmbit="0") odd 2 2 internal memory internal rom/ram sfr area 12 coefficient j, k
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 53 fld controller the m30218 group has fluorescent display (fld) drive and control circuits. table ka-0 shows the fld controller specifications. specification ? 52 pins ( 20 pins can switch general purpose port) ? 4 pins ( 4 pins can switch general purpose port) (a driver must be installed externally) ? used fld output 28 segment x 28 digit (segment number + digit number 56) ? used digit output 40 segment x 16 digit (segment number 40, digit number 16) ? connected to m35501 56 segment x (connect number of m35501) digit (segment number 56, digit number number of m35501 x 16) ? used p4 4 to p4 7 expansion 52 segment x 16 digit (segment number 52, digit number 16) ? 3.2 m s to 819.2 m s (count source x in /32,10mhz) ? 12.8 m s to 3276.8 m s (count source x in /128,10mhz) ? 3.2 m s to 819.2 m s (count source x in /32,10mhz) ? 12.8 m s to 3276.8 m s (count source x in /128,10mhz) ? digit interrupt ? fld blanking interrupt ? key-scan used digit ? key-scan used segment ? digit pulse output function this function automatically outputs digit pulse. ? m35501 connect function the number of digits can be increased easily by using the output of dim out (p9 7 ) as clk for the m35501. ? toff section generate / not generate function this function does not generate toff1 section when the connected outputs are the same. ? gradation display function this function allows each segment to be set for dark or bright display. ? p4 4 to p4 7 expansion function this function provides 16 lines of digit outputs from four ports by attaching a 4 16 decoder. item fld controller port high-breakdown-volt- age output port cmos port display pixel number period dimmer time interrupt key-scan expand function table ka-0. fld controller specifications
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 54 figure ka-1. block diagram for fld control circuit 03e8 16 035b 16 8 p4 0 /fld 48 p4 1 /fld 49 p4 2 /fld 50 p4 3 /fld 51 p4 4 /fld 52 p4 5 /fld 53 p4 6 /fld 54 p4 7 /fld 55 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 0500 16 05df 16 03e1 16 8 p1 0 /fld 24 p1 1 /fld 25 p1 2 /fld 26 p1 3 /fld 27 p1 4 /fld 28 p1 5 /fld 29 p1 6 /fld 30 p1 7 /fld 31 main address bus local address bus fld automatic display ram p6 0 /fld 0 p6 1 /fld 1 p6 2 /fld 2 p6 3 /fld 3 p6 4 /fld 4 p6 5 /fld 5 p6 6 /fld 6 p6 7 /fld 7 035d 16 8 03e9 16 8 p5 0 /fld 8 p5 1 /fld 9 p5 2 /fld 10 p5 3 /fld 11 p5 4 /fld 12 p5 5 /fld 13 p5 6 /fld 14 p5 7 /fld 15 main data bus local data bus fld blanking interrupt fld digit interrupt fldc mode register (0350 16 ) fld data pointer reload register (0358 16 ) fld data pointer (0358 16 ) timing generator address decoder 03e4 16 0359 16 8 p2 0 /fld 32 p2 1 /fld 33 p2 2 /fld 34 p2 3 /fld 35 p2 4 /fld 36 p2 5 /fld 37 p2 6 /fld 38 p2 7 /fld 39 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 03e5 16 035a 16 8 p3 0 /fld 40 p3 1 /fld 41 p3 2 /fld 42 p3 3 /fld 43 p3 4 /fld 44 p3 5 /fld 45 p3 6 /fld 46 p3 7 /fld 47 fld/p fld/p fld/p fld/p fld/p fld/p fld/p fld/p 03e0 16 8 p0 0 /fld 16 p0 1 /fld 17 p0 2 /fld 18 p0 3 /fld 19 p0 4 /fld 20 p0 5 /fld 21 p0 6 /fld 22 p0 7 /fld 23 dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld dig/fld 035c 16 03ec 16 fld/port switch register digit output set register
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 55 figure ka-2. fldc-related register(1) f l d c m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t f l d m0 3 5 0 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 a u t o m a t i c d i s p l a y c o n t r o l b i t 0 : g e n e r a l - p u r p o s e m o d e 1 : a u t o m a t i c d i s p l a y m o d e f l d m 0 f l d m 1 f l d m 2 f l d m 3 d i s p l a y s t a r t b i t0 : s t o p d i s p l a y 1 : d i s p l a y ( s t a r t t o d i s p l a y b y s w i t c h i n g 0 t o 1 ) t s c a n c o n t r o l b i t s 0 0 : f l d d i g i t i n t e r r u p t ( a t r i s i n g e d g e o f e a c h d i g i t ) 0 1 : 1 x t d i s p 1 0 : 2 x t d i s p 1 1 : 3 x t d i s p 0 : 1 6 t i m i n g m o d e 1 : 3 2 t i m i n g m o d e t i m i n g n u m b e r c o n t r o l b i t g r a d a t i o n d i s p l a y m o d e s e l e c t i o n c o n t r o l b i t 0 : n o t s e l e c t i n g 1 : s e l e c t i n g ( n o t e ) f l d m 4 f l d m 5 n o t e : w h e n a g r a d a t i o n d i s p l a y m o d e i s s e l e c t e d , a n u m b e r o f t i m i n g i s m a x . 1 6 t i m i n g . ( s e t t h e t i m i n g n u m b e r c o n t r o l b i t t o 0 . ) t d i s p c o u n t e r c o u n t s o u r c e s e l e c t i o n b i t 0 : f ( x i n ) / 3 2 1 : f ( x i n ) / 1 2 8 f l d m 6 h i g h - b r e a k d o w n v o l t a g e p o r t d r i v a b i l i t y s e l e c t b i t 0 : d r i v a b i l i t y s t r o n g 1 : d r i v a b i l i t y w e a k f l d m 7 f l d o u t p u t c o n t r o l r e g i s t e r s y m b o la d d r e s sw h e n r e s e t f l d c o n0 3 5 1 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 f l d c o n 7 f l d c o n 5 f l d c o n 4 f l d c o n 2 f l d c o n0 f l d c o n 6 p 4 4 t o p 4 7 f l d o u t p u t r e v e r s e b i t p 4 4 t o p 4 7 f l d t o f f i s i n v a l i d b i t 0 : p e r f o r m n o r m a l l y 1 : t o f f i s i n v a l i d p 9 7 d i m m e r o u t p u t c o n t r o l b i t 0 : o u t p u t n o r m a l l y 1 : d i m m e r o u t p u t c m o s p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 0 : s e c t i o n o f t o f f d o e s n o t g e n e r a t e 1 : s e c t i o n o f t o f f g e n e r a t e s h i g h - b r e a k d o w n - v o l t a g e p o r t s : s e c t i o n o f t o f f g e n e r a t e / n o t g e n e r a t e b i t 0 : s e c t i o n o f t o f f d o e s n o t g e n e r a t e 1 : s e c t i o n o f t o f f g e n e r a t e s t o f f 2 s e t / r e s e t c h a n g e b i t 0 : g r a d a t i o n d i s p l a y d a t a i s r e s e t a t t o f f 2 ( s e t a t t o f f 1 ) 1 : g r a d a t i o n d i s p l a y d a t a i s s e t a t t o f f 2 ( r e s e t a t t o f f 1 ) w r 0 : o u t p u t n o r m a l l y 1 : r e v e r s e o u t p u t n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e 0 . t d i s p t i m e s e t r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t d i s p0 3 5 2 1 6 0 0 1 6 v a l u e s t h a t c a n b e s e t b 7b 0 c o u n t s t d i s p t i m e . c o u n t s o u r c e i s s e l e c t e d b y t d i s p c o u n t e r c o u n t s o u r c e s e l e c t b i t . w r 0 1 6 t o f f 1 6 f u n c t i o n f l d b l a n k i n g i n t e r r u p t ( a t f a l l i n g e d g e o f l a s t d i g i t ) } b 3 b 2 w r
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 56 figure ka-2a. fldc-related register(2) toff1 time set register symbol address when reset toff1 0354 16 ff 16 w r b7 b0 function values that can be set counts toff1 time. count source is selected by tdisp counter count source select bit. 3 to ff 16 toff2 time set register symbol address when reset toff2 0356 16 ff 16 w r b7 b0 counts toff2 time. count source is selected by tdisp counter count source select bit. 3 to ff 16 fld data pointer symbol address when reset flddp 0358 16 indeterminate w r b7 b0 counts fld output timing. set this register to ?ld output data - 1 ? 1 to 1f 16 note: reading the fld data pointer takes out the count at that moment. 0 : normal port 1 : fld output port port p2 fld / port switch register symbol address when reset p2fpr 0359 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p2fpr0 p2fpr2 p2fpr1 p2fpr3 p2fpr4 p2fpr6 p2fpr5 p2fpr7 port p2 0 fld/port switch bit 0 : normal port 1 : fld output port port p2 1 fld/port switch bit 0 : normal port 1 : fld output port port p2 2 fld/port switch bit 0 : normal port 1 : fld output port port p2 3 fld/port switch bit 0 : normal port 1 : fld output port port p2 4 fld/port switch bit 0 : normal port 1 : fld output port port p2 5 fld/port switch bit 0 : normal port 1 : fld output port port p2 6 fld/port switch bit 0 : normal port 1 : fld output port port p2 7 fld/port switch bit function values that can be set function values that can be set bit name function bit symbol a a aa aa a aa a aa a aa a aa a aa a aa a a aa aa a a aa aa a aa a aa
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 57 figure ka-2b. fldc-related register(3) 0 : normal port 1 : fld output port port p3 fld / port switch register symbol address when reset p3fpr 035a 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p3fpr0 p3fpr2 p3fpr1 p3fpr3 p3fpr4 p3fpr6 p3fpr5 p3fpr7 port p3 0 fld/port switch bit 0 : normal port 1 : fld output port port p3 1 fld/port switch bit 0 : normal port 1 : fld output port port p3 2 fld/port switch bit 0 : normal port 1 : fld output port port p3 3 fld/port switch bit 0 : normal port 1 : fld output port port p3 4 fld/port switch bit 0 : normal port 1 : fld output port port p3 5 fld/port switch bit 0 : normal port 1 : fld output port port p3 6 fld/port switch bit 0 : normal port 1 : fld output port port p3 7 fld/port switch bit bit name function bit symbol a a a a a a a a a a a a a a a a a a a a 0 : normal port 1 : fld output port port p4 fld / port switch register symbol address when reset p4fpr 035b 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p4fpr0 p4fpr2 p4fpr1 p4fpr3 p4fpr4 p4fpr6 p4fpr5 p4fpr7 port p4 0 fld/port switch bit 0 : normal port 1 : fld output port port p4 1 fld/port switch bit 0 : normal port 1 : fld output port port p4 2 fld/port switch bit 0 : normal port 1 : fld output port port p4 3 fld/port switch bit 0 : normal port 1 : fld output port port p4 4 fld/port switch bit 0 : normal port 1 : fld output port port p4 5 fld/port switch bit 0 : normal port 1 : fld output port port p4 6 fld/port switch bit 0 : normal port 1 : fld output port port p4 7 fld/port switch bit bit name function bit symbol a a a a a a a a a a a a a a a a a a a a 0 : fld output 1 : digit output port p5 digit output set register symbol address when reset p5dor 035c 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p5dor0 p5dor2 p5dor1 p5dor3 p5dor4 p5dor6 p5dor5 p5dor7 port p5 0 fld/digit switch bit 0 : fld output 1 : digit output port p5 1 fld/digit switch bit 0 : fld output 1 : digit output port p5 2 fld/digit switch bit 0 : fld output 1 : digit output port p5 3 fld/digit switch bit 0 : fld output 1 : digit output port p5 4 fld/digit switch bit 0 : fld output 1 : digit output port p5 5 fld/digit switch bit 0 : fld output 1 : digit output port p5 6 fld/digit switch bit 0 : fld output 1 : digit output port p5 7 fld/digit switch bit bit name function bit symbol a a a a a a a a a a a a a a a a a a a a a a
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 58 figure ka-2c. fldc-related register(4) 0 : fld output 1 : digit output port p6 digit output set register symbol address when reset p6dor 035d 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 p6dor0 p6dor2 p6dor1 p6dor3 p6dor4 p6dor6 p6dor5 p6dor7 port p6 0 fld/digit switch bit 0 : fld output 1 : digit output port p6 1 fld/digit switch bit 0 : fld output 1 : digit output port p6 2 fld/digit switch bit 0 : fld output 1 : digit output port p6 3 fld/digit switch bit 0 : fld output 1 : digit output port p6 4 fld/digit switch bit 0 : fld output 1 : digit output port p6 5 fld/digit switch bit 0 : fld output 1 : digit output port p6 6 fld/digit switch bit 0 : fld output 1 : digit output port p6 7 fld/digit switch bit bit name function bit symbol a a a a a a a a a a a a a a a a a a a a a a
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 59 figure ka-3. segment/digit setting example fld automatic display pins p0 to p6 are the pins capable of automatic display output for the fld. the fld start operating by setting the automatic display control bit (bit 0 at address 0350 16 ) to 1. there is the fld output function that outputs ram contents from the port every timing or the digit output function that drives the port high with digit timing. the fld can be displayed using the fld output for the segments and the digit or fld output for the digits. when using the fld output for the digits, be sure to write digit display patterns to the ram in advance. the remaining segment and digit lines can be used as general-purpose ports. settings of each port are shown below. table ka-1. pins in fld automatic display mode port name automatic display pins setting method p5, p6 fld 0 to fld 15 p0, p1 fld 16 to fld 31 p2, p3, fld 32 to fld 51 p4 4 to p4 3 p4 4 to p4 7 fld 52 to fld 55 the individual bits of the digit output set register (address 035c 16 , 035d 16 ) can set each pin either fld port (0) or digit port (1). when the pins are set for the digit port, the digit pulse output func- tion is enabled, so the digit pulses can always be output regardless the value of fld automatic display ram. fld exclusive use port (automatic display control bit (bit 0 of ad- dress 0350 16 )=1) the individual bits of the fld/port switch register (addresses 0359 16 to 035b 16 ) can set each pin to either fld port (1) or gen- eral-purpose port (0). the individual bits of the fld/port switch register (address 035b 16 ) can set each pin to either fld port (1) or general-purpose port (0). the digit pulse output function turns to available, and the digit pulse can output by setting of the fld output set register (address 0351 16 ). the port output format is the cmos output. when using the port as a display pin, a driver must be installed externally. port p5 port p0 number of segments number of digits port p6 36 16 port p1 setting example 1 shown below is a register setup example where only fld output is used. in this case, the digit display output pattern must be set in the fld automatic display ram in advance. 1 1 1 1 1 1 1 1 fld 32 (seg output) fld 33 (seg output) fld 34 (seg output) fld 35 (seg output) fld 36 (seg output) fld 37 (seg output) fld 38 (seg output) fld 39 (seg output) fld 16 (seg output) fld 17 (seg output) fld 18 (seg output) fld 19 (seg output) fld 20 (seg output) fld 21 (seg output) fld 22 (seg output) fld 23 (seg output) fld 0 (dig output ) fld 1 (dig output) fld 2 (dig output) fld 3 (dig output) fld 4 (dig output) fld 5 (dig output) fld 6 (dig output) fld 7 (dig output) 0 0 0 0 0 0 0 0 fld 8 (dig output) fld 9 (dig output) fld 10 (dig output) fld 11 (dig output) fld 12 (dig output) fld 13 (dig output) fld 14 (dig output) fld 15 (dig output) 0 0 0 0 0 0 0 0 fld 24 (seg output) fld 25 (seg output) fld 26 (seg output) fld 27 (seg output) fld 28 (seg output) fld 29 (seg output) fld 30 (seg output) fld 31 (seg output) port p2 1 1 1 1 1 1 1 1 fld 40 (seg output) fld 41 (seg output) fld 42 (seg output) fld 43 (seg output) fld 44 (seg output) fld 45 (seg output) fld 46 (seg output) fld 47 (seg output) port p3 1 1 1 1 0 0 0 0 fld 48 (seg output) fld 49 (seg output) fld 50 (seg output) fld 51 (seg output) fld 52 (port output) fld 53 (port output) fld 54 (port output) fld 55 (port output) port p4 port p5 port p0 port p6 28 12 port p1 setting example 2 shown below is a register setup example where both fld output and digit waveform output are used. in this case, because the digit display output is automatically generated, there is no need to set the display pattern in the fld automatic display ram. 1 1 1 1 1 1 1 1 fld 32 (seg output) fld 33 (seg output) fld 34 (seg output) fld 35 (seg output) fld 36 (seg output) fld 37 (seg output) fld 38 (seg output) fld 39 (seg output) fld 16 (seg output) fld 17 (seg output) fld 18 (seg output) fld 19 (seg output) fld 20 (seg output) fld 21 (seg output) fld 22 (seg output) fld 23 (seg output) fld 0 (dig output) fld 1 (dig output) fld 2 (dig output) fld 3 (dig output) fld 4 (dig output) fld 5 (dig output) fld 6 (dig output) fld 7 (dig output) 1 1 1 1 1 1 1 1 fld 8 (dig output) fld 9 (dig output) fld 10 (dig output) fld 11 (dig output) fld 12 (seg output) fld 13 (seg output) fld 14 (seg output) fld 15 (seg output) 1 1 1 1 0 0 0 0 fld 24 (seg output) fld 25 (seg output) fld 26 (seg output) fld 27 (seg output) fld 28 (seg output) fld 29 (seg output) fld 30 (seg output) fld 31 (seg output) port p2 1 1 1 1 0 0 0 0 fld 40 (seg output) fld 41 (seg output) fld 42 (seg output) fld 43 (seg output) fld 44 (port output) fld 45 (port output) fld 46 (port output) fld 47 (port output) port p3 0 0 0 0 0 0 0 0 fld 48 (port output) fld 49 (port output) fld 50 (port output) fld 51 (port output) fld 52 (port output) fld 53 (port output) fld 54 (port output) fld 55 (port output) port p4 dig output : this output is connected to digit of the fld. seg output : this output is connected to segment of the fld. port output : this output is g eneral-purpose port ( used pro g ram). dig output : this output is connected to digit of the fld. seg output : this output is connected to segment of the fld. port output : this output is general-purpose port ( used program). the contents of digit output set register (035c 16 , 035d 16 ) fld/port switch register (0359 16 , 035b 16 ) number of segments number of digits the contents of digit output set register (035c 16 , 035d 16 ) fld/port switch register (0359 16 , 035b 16 )
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 60 fld automatic display ram the fld automatic display ram uses the 224 bytes of addresses 0500 16 to 05df 16 . for fld, the 3 modes of 16-timing ordinary mode, 16-timing?gradation display mode and 32-timing mode are available depending on the number of timings and the use/not use of gradation display. the automatic display ram in each mode is as follows: (1) 16-timing?ordinary mode this mode is used when the display timing is 16 or less. the 112 bytes of addresses 0570 16 to 05df 16 are used as a fld display data store area. because addresses 0500 16 to 056f 16 are not used as the automatic display ram, they can be the ordinary ram. (2) 16-timing?gradation display mode this mode is used when the display timing is 16 or less, in which mode each segment can be set for dark or bright display. the 224 bytes of addresses 0500 16 to 05df 16 are used. the 112 bytes of addresses 0570 16 to 05df 16 are used as an fld display data store area, while the 112 bytes of addresses 0500 16 to 056f 16 are used as a gradation display control data store area. (3) 32-timing mode this mode is used when the display timing is 16 or greater. this mode can be used for up to 32-timing. the 224 bytes of addresses 0500 16 to 05df 16 are used as an fld display data store area. the fld data pointer (address 0358 16 ) is a register to count display timings. this pointer has a reload register and when the terminal count is reached, it starts counting over again after being reloaded with the initial count. make sure the timing count C 1 is set to the fld data pointer. when writing data to this address, the data is written to the fld data pointer reload register; when reading data from this address, the value in the fld data pointer is read. figure ka-4. fld automatic display ram assignment 16-timing?rdinary mode 05df 16 0570 16 0500 16 05df 16 0500 16 05df 16 0570 16 0500 16 16-timing?radation display mode 32-timing mode 1 to 32 timing display data stored area gradation display control data stored area 1 to 16 timing display data stored area 1 to 16 timing display data stored area not used
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 61 data setup (1) 16-timing?ordinary mode the area of addresses 0570 16 to 05df 16 are used as a fld automatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p4 is stored at address 0570 16 , the last data of fld port p3 is stored at address 0580 16 , the last data of fld port p2 is stored at address 0590 16 , the last data of fld port p1 is stored at address 05a0 16 , the last data of fld port p0 is stored at address 05b0 16 , the last data of fld port p5 is stored at address 05c0 16 , and the last data of fld port p6 is stored at address 05d0 16 , to assign in sequence from the last data respectively. the first data of the fld port p4, p3, p2, p1, p0, p5, and p6 is stored at an address which adds the value of (the timing number C 1) to the corresponding address 0570 16 , 0580 16 , 0590 16 , 05a0 16 , 05b0 16 , 05c0 16 and 05df 16 . set the fld data pointer reload register to the value given by the number of digits C 1. (2) 16-timing?gradation display mode display data setting is performed in the same way as that of the 16-timing?ordinary mode. gradation display control data is arranged at an address resulting from subtracting 0070 16 from the display data store address of each timing and pin. bright display is performed by setting 0, and dark display is performed by setting 1 . (3) 32-timing mode the area of addresses 0500 16 to 05df 16 are used as a fld automatic display ram. when data is stored in the fld automatic display ram, the last data of fld port p4 is stored at address 0500 16 , the last data of fld port p3 is stored at address 0520 16 , the last data of fld port p2 is stored at address 0540 16 , the last data of fld port p1 is stored at address 0560 16 , the last data of fld port p0 is stored at address 0580 16 , the last data of fld port p5 is stored at address 05a0 16 , and the last data of fld port p6 is stored at address 05c0 16 , to assign in sequence from the last data respectively . the first data of the fld port p4, p3, p2, p0, p1, p5, and p6 is stored at an address which adds the value of (the timing number C 1) to the corresponding address 0500 16 , 0520 16 , 0540 16 , 0560 16 , 0580 16 , 05a0 16 and 05c0 16 . set the fld data pointer reload register to the value given by the number of digits - 1. figure ka-5. example of using the fld automatic display ram in 16-timing?ordinary mode number of timing: 8 (fld data pointer reload register = 7) address 058f 16 0571 16 0572 16 0573 16 0574 16 0575 16 0576 16 0577 16 0578 16 0579 16 057a 16 057b 16 057c 16 057d 16 057e 16 057f 16 0580 16 0581 16 0582 16 0583 16 0584 16 0585 16 0586 16 0587 16 0588 16 0589 16 058a 16 058b 16 058c 16 058d 16 058e 16 0590 16 0591 16 0592 16 0593 16 0594 16 0595 16 0596 16 0597 16 0598 16 0599 16 059a 16 059b 16 059c 16 059d 16 059e 16 059f 16 05a1 16 05a2 16 05a3 16 05a4 16 05a5 16 05a6 16 05a7 16 05a8 16 05a9 16 05aa 16 05ab 16 05ac 16 05ad 16 05ae 16 05af 16 05a0 16 0570 16 the last timing (the last data of fldp4) timing for start (the first data of fldp4) the last timing (the last data of fldp3) timing for start (the first data of fldp3) the last timing (the last data of fldp2) timing for start (the first data of fldp2) the last timing (the last data of fldp1) timing for start (the first data of fldp1) 76543210 bit address 05b1 16 05b2 16 05b3 16 05b4 16 05b5 16 05b6 16 05b7 16 05b8 16 05b9 16 05ba 16 05bb 16 05bc 16 05bd 16 05be 16 05bf 16 05b0 16 the last timing (the last data of fldp0) fldp0 data area timing for start (the first data of fldp0) 76543210 bit 05c1 16 05c2 16 05c3 16 05c4 16 05c5 16 05c6 16 05c7 16 05c8 16 05c9 16 05ca 16 05cb 16 05cc 16 05cd 16 05ce 16 05cf 16 05c0 16 05d1 16 05d2 16 05d3 16 05d4 16 05d5 16 05d6 16 05d7 16 05d8 16 05d9 16 05da 16 05db 16 05dc 16 05dd 16 05de 16 05df 16 05d0 16 the last timing (the last data of fldp5) fldp5 data area timing for start (the first data of fldp5) the last timing (the last data of fldp6) fldp6 data area timing for start (the first data of fldp6) fldp1 data area fldp2 data area fldp4 data area fldp3 data area
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 62 figure ka-6. example of using the fld automatic display ram in 16-timing?gradation display mode number of timing: 15 (fld data pointer reload register = 14) address 058f 16 0571 16 0572 16 0573 16 0574 16 0575 16 0576 16 0577 16 0578 16 0579 16 057a 16 057b 16 057c 16 057d 16 057e 16 057f 16 0580 16 0581 16 0582 16 0583 16 0584 16 0585 16 0586 16 0587 16 0588 16 0589 16 058a 16 058b 16 058c 16 058d 16 058e 16 0590 16 0591 16 0592 16 0593 16 0594 16 0595 16 0596 16 0597 16 0598 16 0599 16 059a 16 059b 16 059c 16 059d 16 059e 16 059f 16 05a1 16 05a2 16 05a3 16 05a4 16 05a5 16 05a6 16 05a7 16 05a8 16 05a9 16 05aa 16 05ab 16 05ac 16 05ad 16 05ae 16 05af 16 05a0 16 05b1 16 05b2 16 05b3 16 05b4 16 05b5 16 05b6 16 05b7 16 05b8 16 05b9 16 05ba 16 05bb 16 05bc 16 05bd 16 05be 16 05bf 16 05b0 16 0570 16 the last timing (the last data of fldp4) 76543210 bit the last timing (the last data of fldp3) the last timing (the last data of fldp2) the last timing (the last data of fldp1) the last timing (the last data of fldp0) fldp4 data area fldp3 data area fldp2 data area fldp1 data area fldp0 data area 05c1 16 05c2 16 05c3 16 05c4 16 05c5 16 05c6 16 05c7 16 05c8 16 05c9 16 05ca 16 05cb 16 05cc 16 05cd 16 05ce 16 05cf 16 05c0 16 the last timing (the last data of fldp5) fldp5 data area 05d1 16 05d2 16 05d3 16 05d4 16 05d5 16 05d6 16 05d7 16 05d8 16 05d9 16 05da 16 05db 16 05dc 16 05dd 16 05de 16 05df 16 05d0 16 the last timing (the last data of fldp6) fldp6 data area address 051f 16 0501 16 0502 16 0503 16 0504 16 0505 16 0506 16 0507 16 0508 16 0509 16 050a 16 050b 16 050c 16 050d 16 050e 16 050f 16 0510 16 0511 16 0512 16 0513 16 0514 16 0515 16 0516 16 0517 16 0518 16 0519 16 051a 16 051b 16 051c 16 051d 16 051e 16 0520 16 0521 16 0522 16 0523 16 0524 16 0525 16 0526 16 0527 16 0528 16 0529 16 052a 16 052b 16 052c 16 052d 16 052e 16 052f 16 0531 16 0532 16 0533 16 0534 16 0535 16 0536 16 0537 16 0538 16 0539 16 053a 16 053b 16 053c 16 053d 16 053e 16 053f 16 0530 16 0541 16 0542 16 0543 16 0544 16 0545 16 0546 16 0547 16 0548 16 0549 16 054a 16 054b 16 054c 16 054d 16 054e 16 054f 16 0540 16 0500 16 the last timing (the last data of fldp4) 76543210 bit the last timing (the last data of fldp3) the last timing (the last data of fldp2) the last timing (the last data of fldp1) the last timing (the last data of fldp0) fldp4 gradation display data area fldp3 gradation display data area fldp2 gradation display data area fldp1 gradation display data area fldp0 gradation display data area 0551 16 0552 16 0553 16 0554 16 0555 16 0556 16 0557 16 0558 16 0559 16 055a 16 055b 16 055c 16 055d 16 055e 16 055f 16 0550 16 the last timing (the last data of fldp5) fldp5 gradation display data area 0561 16 0562 16 0563 16 0564 16 0565 16 0566 16 0567 16 0568 16 0569 16 056a 16 056b 16 056c 16 056d 16 056e 16 056f 16 0560 16 the last timing (the last data of fldp6) fldp6 gradation display data area timing for start (the first data of fldp4) timing for start (the first data of fldp3) timing for start (the first data of fldp2) timing for start (the first data of fldp1) timing for start (the first data of fldp0) timing for start (the first data of fldp5) timing for start (the first data of fldp6) timing for start (the first data of fldp4) timing for start (the first data of fldp3) timing for start (the first data of fldp2) timing for start (the first data of fldp1) timing for start (the first data of fldp0) timing for start (the first data of fldp5) timing for start (the first data of fldp6)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 63 figure ka-7. example of using the fld automatic display ram in 32-timing mode number of timing: 20 (fld data pointer reload register = 19) address 058f 16 0571 16 0572 16 0573 16 0574 16 0575 16 0576 16 0577 16 0578 16 0579 16 057a 16 057b 16 057c 16 057d 16 057e 16 057f 16 0580 16 0581 16 0582 16 0583 16 0584 16 0585 16 0586 16 0587 16 0588 16 0589 16 058a 16 058b 16 058c 16 058d 16 058e 16 0590 16 0591 16 0592 16 0593 16 0594 16 0595 16 0596 16 0597 16 0598 16 0599 16 059a 16 059b 16 059c 16 059d 16 059e 16 059f 16 05a1 16 05a2 16 05a3 16 05a4 16 05a5 16 05a6 16 05a7 16 05a8 16 05a9 16 05aa 16 05ab 16 05ac 16 05ad 16 05ae 16 05af 16 05a0 16 05b1 16 05b2 16 05b3 16 05b4 16 05b5 16 05b6 16 05b7 16 05b8 16 05b9 16 05ba 16 05bb 16 05bc 16 05bd 16 05be 16 05bf 16 05b0 16 0570 16 76543210 bit fldp0 data area 05c1 16 05c2 16 05c3 16 05c4 16 05c5 16 05c6 16 05c7 16 05c8 16 05c9 16 05ca 16 05cb 16 05cc 16 05cd 16 05ce 16 05cf 16 05c0 16 the last timing (the last data of fldp5) fldp5 data area 05d1 16 05d2 16 05d3 16 05d4 16 05d5 16 05d6 16 05d7 16 05d8 16 05d9 16 05da 16 05db 16 05dc 16 05dd 16 05de 16 05df 16 05d0 16 the last timing (the last data of fldp6) fldp6 data area address 051f 16 0501 16 0502 16 0503 16 0504 16 0505 16 0506 16 0507 16 0508 16 0509 16 050a 16 050b 16 050c 16 050d 16 050e 16 050f 16 0510 16 0511 16 0512 16 0513 16 0514 16 0515 16 0516 16 0517 16 0518 16 0519 16 051a 16 051b 16 051c 16 051d 16 051e 16 0520 16 0521 16 0522 16 0523 16 0524 16 0525 16 0526 16 0527 16 0528 16 0529 16 052a 16 052b 16 052c 16 052d 16 052e 16 052f 16 0531 16 0532 16 0533 16 0534 16 0535 16 0536 16 0537 16 0538 16 0539 16 053a 16 053b 16 053c 16 053d 16 053e 16 053f 16 0530 16 0541 16 0542 16 0543 16 0544 16 0545 16 0546 16 0547 16 0548 16 0549 16 054a 16 054b 16 054c 16 054d 16 054e 16 054f 16 0540 16 0500 16 the last timing (the last data of fldp4) 76543210 bit the last timing (the last data of fldp3) the last timing (the last data of fldp2) the last timing (the last data of fldp1) the last timing (the last data of fldp0) fldp4 data area fldp3 data area fldp2 data area fldp1 data area 0551 16 0552 16 0553 16 0554 16 0555 16 0556 16 0557 16 0558 16 0559 16 055a 16 055b 16 055c 16 055d 16 055e 16 055f 16 0550 16 0561 16 0562 16 0563 16 0564 16 0565 16 0566 16 0567 16 0568 16 0569 16 056a 16 056b 16 056c 16 056d 16 056e 16 056f 16 0560 16 timing for start (the first data of fldp0) timing for start (the first data of fldp5) timing for start (the first data of fldp6) timing for start (the first data of fldp4) timing for start (the first data of fldp3) timing for start (the first data of fldp2) timing for start (the first data of fldp1)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 64 figure ka-11. fldc timing toff1 tdisp toff1 toff2 tdisp ?rayscale display mode is not selected (address 0350 16 bit 5 = ?? ?rayscale display mode is selected and set for bright display (address 0350 16 bit 5 = ??and the corresponding grayscale display control data = ?? low output period for blurring prevention display output period display output period low output period for blurring prevention ?rayscale display mode is selected and set for dark display (address 0350 16 bit 5 = ??and the corresponding grayscale display control data = ?? low output period for dark display timing setting each timing is set by the fldc mode register, tdisp time set register, toff1 time set register, and toff2 time set register. ?tdisp time setting the tdisp time represents the length of display timing. in non-gradation display mode, it consists of a fld display output period and a toff1 time. in gradation display mode, it consists of the display output period and toff1 time plus a low signal output period for dark display. set the tdisp time by the tdisp counter count source select bit of the fldc mode register and the tdisp time set register. supposing that the value of the tdisp time set register is n, the tdisp time is represented as tdisp = (n+1) x t (t: count source). when the tdisp counter count source select bit of the fldc mode register is 0 and the value of the tdisp time set register is 200 (c8 16 ), the tdisp time is: tdisp = (200+1) x 3.2 (at x in = 10 mhz) = 643 m s. when reading the tdisp time set register, the value in the counter is read out. ?toff1 time setting the toff1 time represents a non-output (low signal output) time to prevent blurring of fld, and to dim the display. use the toff1 time set register to set this toff1 time. make sure the value set to toff1 is smaller than tdisp and toff2. supposing that the value of the toff1 time set register is n1, the toff1 time is represented as toff1 = n1 x t. when the tdisp counter count source select bit of the fldc mode register is 0 and the value of the toff1 time set register is 30 (1e 16 ), toff1 = 30 x 3.2 (at x in = 10 mhz) = 96 m s. ?toff2 time setting the toff2 time is provided for dark display. for bright display, the fld display output remains effective until the counter that is counting tdisp reaches the terminal count. for dark display, however, l (or off) signal is output when the counter that is counting toff2 reaches the terminal count. this toff2 time setting is valid only for fld ports which are in the gradation display mode and whose gradation display control ram value is 1 . set the toff2 time by the toff2 time set register. make sure the value set to toff2 is smaller than tdisp but larger than toff1. supposing that the value of the toff2 time set register is n2, the toff2 time is repre- sented as toff2 = n2 x t. when the tdisp counter count source select bit of the fldc mode register is 0 and the value of the toff2 time set register is 180 (b4 16 ), toff2 = 180 x 3.2 (at x in = 10 mhz) = 576 m s.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 65 figure ka-12a. timing using digit interrupt fld digit output tdisp repeat synchronous tn tn-1 tn-2 t4 t3 t2 t1 tn tn-1 tn-2 t4 toff1 fld digit interrupt generated at the rising edge of digit ( each timing) fld automatic display start automatic display starts by setting both the automatic display control bit (bit 0 of address 0350 16 ) and the display start bit (bit 1 of address 0350 16 ) to 1. the ram content at a location apart from the start address of the automatic display ram for each port by (fld data pointer (address 0358 16 ) C 1) is output to each port. the fld data pointer (address 0358 16 ) counts down in the tdisp interval. when the count ff 16 is reached, the pointer is reloaded and starts counting over again. before setting the display start bit (bit 1 of address 0350 16 ) to 1, be sure to set the fld/port switch register, fld/dig switch register, fldc mode register, tdisp time set register, toff1 time set register, toff2 time set register, and fld data pointer. during fld automatic display, bit 1 of the fldc mode register (address 0350 16 ) always keeps 1, and fld automatic display can be interrupted by writing 0 to bit 1. key-scan and interrupt either a fld digit interrupt or fld blanking interrupt can be selected using the tscan control bits (bits 2, 3 of address 0350 16 ). the fld digit interrupt is generated when the toff1 time in each timing expires (at rising edge of digit output). key scanning that makes use of fld digits can be achieved using each fld digit interrupt. to use fld digit interrupts for key scanning, follow the procedure described below. (1) read the port value each time the interrupt occurs. (2) the key is fixed on the last digit interrupt. the digit positions output can be determined by reading the fld data pointer (address 0358 16 ).
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 66 figure ka-12b. timing using fld blanking interrupt tdisp tscan tn tn-1 tn-2 t4 t3 t2 t1 tn tn-1 tn-2 segment setting by software fld blanking interrupt generated at the falling of edge of the last digit fld digit output repeat synchronous the fld blanking interrupt is generated when the fld data pointer (address 0358 16 ) reaches ff 16 . the fld automatic display output is turned off for a duration of 1 x tdisp, 2 x tdisp, or 3 x tdisp depending on post-interrupt settings. during this time, key scanning that makes use of fld segments can be achieved. when a key-scan is performed with the segment during key-scan blanking period tscan, take the following sequence: 1. write 0 to bit 0 of the fldc mode register (address 0350 16 ). 2. set the port corresponding to the segment for key-scan to the output port. 3. perform the key-scan. 4. after the key-scan is performed, write 1 to bit 0 of fldc mode register (address 0350 16 ). ?note: when performing a key-scan according to the above steps 1 to 4, take the following points into consideration. 1. do not set 0 in bit 1 of the fldc mode register (address 0350 16 ). 2. do not set 1 in the ports corresponding to digits.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 67 p4 4 to p4 7 expansion function p4 4 to p4 7 are cmos output-type ports. fld digit outputs can be increased as many as 16 lines by con- necting a 4-bit to 16-bit decoder to these ports. p4 4 to p4 7 have the function to allow for connection to a 4- bit to 16-bit decoder. (1) p4 4 to p4 7 toff invalid function this function disables the toff1 time and toff2 time and outputs display data for the duration of tdisp. (see figure ka-13.) this can be accomplished by setting the p4 4 to p4 7 toff disable bit (address 0350 16 bit 2) to 1. unlike the toff section generate/not generate function, this function disables all display data. (2) dimmer signal output function this function allows a dimmer signal creation signal to be output from dim out (p9 7 ). the dimmer function can be materialized by controlling the decoder with this signal. (see figure ka-13.) this function can be set by writing p9 7 dimmer output control bit (bit 4 of address 0351 16 ) to 1. (3) p4 4 to p4 7 fld output reverse bit p4 4 to p4 7 are provided with a function to reverse the polarity of the fld output. this function is useful in adjusting the polarity when using an externally installed driver. the output polarity can be reversed by setting bit 0 of the fld output control register (address 0351 16 ) to 1 . figure ka-13. p 4 to p4 7 fld output pulses tdisp toff2 toff1 for dimmer signal dimout(p9 7 ) fld output ?rayscale display mode is not selected ?rayscale display mode is selected and set for bright display (grayscale display control data = ?? ?rayscale display mode is selected and set for dark display (grayscale display control data = ?? ?rayscale display mode is selected and toff2 set/reset bit is ?? (grayscale display control data = ?? output selecting p4 4 to p4 7 toff invalid
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 68 toff2 set/reset change bit in gradation display mode, the values set by the toff2 time set register (toff2) are effective. when the fld output control register (bit 7 of address 0351 16 ) in the initial state = 0, ram data is output to the fld output ports (set) at the time that is set by toff1 and is turned to 0 (reset) at the time that is set by toff2. when bit 7 = 1, ram data is output (set) at the time that is set by toff2 and is turned to 0 (reset) when the tdisp time expires. toff section generate/not generate function the function is for reduction of useless noises which generated as every switching of ports, because of the combined capacity of among fld ports. in case the continuous data output to each fld ports, the toff1 section of the continuous parts is not generated. (see figure ka-15) if it needs toff1 section on fld pulses, set cmos ports: section of toff generate / not generate bit to 1 and set high-breakdown-voltage ports: section of toff generate / not generate bit to 1 . high-breakdown- voltage ports (p5, p6, p3, p2, p1, p0, p4 0 to p4 3 , total 52 pins) generate toff1 section, by setting high- breakdown-voltage ports: section of toff generate / not generate bit to 1 . the cmos ports ( p4 4 to p4 7 , total 4 pins ) generate toff1 section, by setting high-breakdown-voltage ports: section of toff generate / not generate bit to 1. fig. ka-15. toff section generated/not generated function p1x p2x p1x p2x ??output output waveform when ?igh- breakdown-voltage ports: section of toff generate/not generate bit?bit 6 of 0351 16 ) is ?? tdisp toff1 section of toff1 is not generated because of output is same. output waveform when ?igh- breakdown-voltage ports: section of toff generate/not generate bit?bit 6 of 0351 1 6 ) is ?? ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output ??output section of toff1 is not generated because of output is same.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer fld controller 69 fig. ka-16. digit pulses output function digit pulses output function p5 0 to p5 7 and p6 0 to p6 7 allow digit pulses to be output using the fld/digit switch register. set the digit output set register by writing as many consecutive 1s as the timing count from p6 0 . the contents of fld automatic display ram for the ports that have been selected for digit output are disabled, and the pulse shown in figure ka-16 is output automatically. in gradation display mode use, t off2 time becomes effective for the port which selected digit output. because the contents of fld automatic display ram are disabled, the segment data can be changed easily even when segment data and digit data coexist at the same address in the fld automatic display ram. this function is effective in 16-timing normal mode and 16-timing gradation display mode. if a value is set exceeding the timing count (fld data pointer reload register's set value + 1) for any port, the output of such port is l. low-order 4bits of the data pointer fedc b a 0 1 2 3 4 5 6 7 8 9 p5 7 p5 6 p5 5 p5 4 p5 3 p5 2 p5 1 p5 0 p6 7 p6 6 p6 5 p6 4 p6 3 p6 2 p6 1 p6 0 tdisp toff1
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer 70 timer there are eight 16-bit timers. these timers can be classified by function into timers a (five) and timers b (three). all these timers function independently. figures fb-1 show the block diagram of timers. figure fb-1. timer block diagram ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?timer mode ?one-shot mode ?pwm mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?event counter mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ?timer mode ?pulse width measuring mode ta0 in / ta3 out ta1 in / ta4 out ta2 in / ta0 out ta3 in / ta1 out ta4 in / ta2 out tb0 in tb1 in tb2 in timer a0 timer a1 timer a2 timer a3 timer a4 timer b0 timer b1 timer b2 f 1 f 8 f 32 f c32 timer a0 interrupt timer a1 interrupt timer a2 interrupt timer a3 interrupt timer a4 interrupt timer b0 interrupt timer b1 interrupt timer b2 interrupt noise filter noise filter noise filter noise filter noise filter noise filter noise filter noise filter 1/32 f c32 1/8 1/4 f 1 f 8 f 32 x in x cin clock prescaler reset flag (bit 7 at address 0381 16 ) set to ? reset clock prescaler
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 71 timer a figure fb-2 shows the block diagram of timer a. figures fb-3 to fb-5 show the timer a-related registers. except in event counter mode, timers a0 through a4 all have the same function. use the timer ai mode register (i = 0 to 4) bits 0 and 1 to choose the desired mode. timer a has the four operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer's over flow. ? one-shot timer mode: the timer stops counting when the count reaches 0000 16 . ? pulse width modulation (pwm) mode: the timer outputs pulses of a given width. figure fb-2. block diagram of timer a figure fb-3. timer a-related registers (1) c o u n t e r ( 1 6 ) c o u n t s t a r t f l a g ( a d d r e s s 0 3 8 0 1 6 ) u p c o u n t / d o w n c o u n t t a ia d d r e s s e st a jt a kt a i o u t t i m e r a 00 3 8 7 1 6 0 3 8 6 1 6 t i m e r a 4t i m e r a 1t i m e r a 3 t i m e r a 10 3 8 9 1 6 0 3 8 8 1 6 t i m e r a 0t i m e r a 2t i m e r a 4 t i m e r a 20 3 8 b 1 6 0 3 8 a 1 6 t i m e r a 1t i m e r a 3t i m e r a 0 t i m e r a 30 3 8 d 1 6 0 3 8 c 1 6 t i m e r a 2t i m e r a 4t i m e r a 1 t i m e r a 4 0 3 8 f 1 6 0 3 8 e 1 6 t i m e r a 3t i m e r a 0t i m e r a 2 a l w a y s d o w n c o u n t e x c e p t i n e v e n t c o u n t e r m o d e r e l o a d r e g i s t e r ( 1 6 ) l o w - o r d e r 8 b i t s h i g h - o r d e r 8 b i t s c l o c k s o u r c e s e l e c t i o n t i m e r ( g a t e f u n c t i o n ) t i m e r o n e s h o t p w m f 1 f 8 f 3 2 e x t e r n a l t r i g g e r t a i i n ( i = 0 t o 4 ) t b 2 o v e r f l o w e v e n t c o u n t e r f c 3 2 c l o c k s e l e c t i o n t a j o v e r f l o w ( j = i - 1 . n o t e , h o w e v e r , t h a t j = 4 w h e n i = 0 ) p u l s e o u t p u t t o g g l e f l i p - f l o p t a i o u t ( i = 0 t o 4 ) d a t a b u s l o w - o r d e r b i t s d a t a b u s h i g h - o r d e r b i t s u p / d o w n f l a g d o w n c o u n t ( a d d r e s s 0 3 8 4 1 6 ) t a k o v e r f l o w ( k = i + 1 . n o t e , h o w e v e r , t h a t k = 0 w h e n i = 4 ) p o l a r i t y s e l e c t i o n timer ai mode register symbol address when reset taimr(i=0 to 4) 0396 16 to 039a 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b 1 b0 0 0 : timer mode 0 1 : event counter mode 1 0 : one-shot timer mode 1 1 : pulse width modulation (pwm) mode b1 b0 tck1 mr3 mr2 mr1 tmod1 mr0 tmod0 tck0 function varies with each operation mode count source select bit (function varies with each operation mode) operation mode select bit a a a a a a a a a a a a a a a a a a a a a a a a
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 72 figure fb-4. timer a-related registers (2) t i m e r a 4 u p / d o w n f l a g t i m e r a 3 u p / d o w n f l a g t i m e r a 2 u p / d o w n f l a g t i m e r a 1 u p / d o w n f l a g t i m e r a 0 u p / d o w n f l a g t i m e r a 2 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t t i m e r a 3 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t t i m e r a 4 t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g s e l e c t b i t s y m b o la d d r e s sw h e n r e s e t u d f0 3 8 4 1 6 0 0 1 6 t a 4 p t a 3 p t a 2 p u p / d o w n f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 t a 4 u d t a 3 u d t a 2 u d t a 1 u d t a 0 u d 0 : d o w n c o u n t 1 : u p c o u n t t h i s s p e c i f i c a t i o n b e c o m e s v a l i d w h e n t h e u p / d o w n f l a g c o n t e n t i s s e l e c t e d f o r u p / d o w n s w i t c h i n g c a u s e 0 : t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g d i s a b l e d 1 : t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g e n a b l e d w h e n n o t u s i n g t h e t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g f u n c t i o n , s e t t h e s e l e c t b i t t o 0 s y m b o la d d r e s sw h e n r e s e t t a b s r0 3 8 0 1 6 0 0 1 6 c o u n t s t a r t f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 t i m e r b 2 c o u n t s t a r t f l a g t i m e r b 1 c o u n t s t a r t f l a g t i m e r b 0 c o u n t s t a r t f l a g t i m e r a 4 c o u n t s t a r t f l a g t i m e r a 3 c o u n t s t a r t f l a g t i m e r a 2 c o u n t s t a r t f l a g t i m e r a 1 c o u n t s t a r t f l a g t i m e r a 0 c o u n t s t a r t f l a g 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g t b 2 s t b 1 s t b 0 s t a 4 s t a 3 s t a 2 s t a 1 s t a 0 s s y m b o la d d r e s sw h e n r e s e t t a 00 3 8 7 1 6 , 0 3 8 6 1 6 i n d e t e r m i n a t e t a 10 3 8 9 1 6 , 0 3 8 8 1 6 i n d e t e r m i n a t e t a 20 3 8 b 1 6 , 0 3 8 a 1 6 i n d e t e r m i n a t e t a 30 3 8 d 1 6 , 0 3 8 c 1 6 i n d e t e r m i n a t e t a 40 3 8 f 1 6 , 0 3 8 e 1 6 i n d e t e r m i n a t e b 7b 0b 7b 0 ( b 1 5 ) ( b 8 ) t i m e r a i r e g i s t e r ( n o t e ) w r t i m e r m o d e0 0 0 0 1 6 t o f f f f c o u n t s a n i n t e r n a l c o u n t s o u r c e f u n c t i o n v a l u e s t h a t c a n b e s e t e v e n t c o u n t e r m o d e c o u n t s p u l s e s f r o m a n e x t e r n a l s o u r c e o r t i m e r o v e r f l o w0 0 0 0 1 6 t o f f f f 1 6 o n e - s h o t t i m e r m o d e0 0 0 0 1 6 t o f f f f 1 6 c o u n t s a o n e s h o t w i d t h p u l s e w i d t h m o d u l a t i o n m o d e ( 1 6 - b i t p w m ) f u n c t i o n s a s a 1 6 - b i t p u l s e w i d t h m o d u l a t o r 0 0 1 6 t o f e 1 6 ( b o t h h i g h - o r d e r a n d l o w - o r d e r a d d r e s s e s ) 0 0 0 0 1 6 t o f f f e 1 6 n o t e : r e a d a n d w r i t e d a t a i s i n 1 6 - b i t u n i t s . p u l s e w i d t h m o d u l a t i o n m o d e ( 8 - b i t p w m ) t i m e r l o w - o r d e r a d d r e s s f u n c t i o n s a s a n 8 - b i t p r e s c a l e r a n d h i g h - o r d e r a d d r e s s f u n c t i o n s a s a n 8 - b i t p u l s e w i d t h m o d u l a t o r
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 73 figure fb-5. timer a-related registers (3) s y m b o la d d r e s sw h e n r e s e t c p s r f0 3 8 1 1 6 0 x x x x x x x 2 c l o c k p r e s c a l e r r e s e t f l a g b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 c l o c k p r e s c a l e r r e s e t f l a g 0 : n o e f f e c t 1 : p r e s c a l e r i s r e s e t ( w h e n r e a d , t h e v a l u e i s 0 ) c p s r w r n o t h i n g i s a s s i g n e d . t h e s e b i t s c a n n e i t h e r b e s e t n o r r e s e t . w h e n r e a d , t h e i r c o n t e n t s a r e i n d e t e r m i n a t e . t a 1 t g l s y m b o la d d r e s sw h e n r e s e t t r g s r0 3 8 3 1 6 0 0 1 6 t i m e r a 1 e v e n t / t r i g g e r s e l e c t b i t 0 0 : i n p u t o n t a 1 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 0 o v e r f l o w i s s e l e c t e d 1 1 : t a 2 o v e r f l o w i s s e l e c t e d t r i g g e r s e l e c t r e g i s t e r b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : i n p u t o n t a 2 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 1 o v e r f l o w i s s e l e c t e d 1 1 : t a 3 o v e r f l o w i s s e l e c t e d 0 0 : i n p u t o n t a 3 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 2 o v e r f l o w i s s e l e c t e d 1 1 : t a 4 o v e r f l o w i s s e l e c t e d 0 0 : i n p u t o n t a 4 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 3 o v e r f l o w i s s e l e c t e d 1 1 : t a 0 o v e r f l o w i s s e l e c t e d t i m e r a 2 e v e n t / t r i g g e r s e l e c t b i t t i m e r a 3 e v e n t / t r i g g e r s e l e c t b i t t i m e r a 4 e v e n t / t r i g g e r s e l e c t b i t w r t a 1 t g h t a 2 t g l t a 2 t g h t a 3 t g l t a 3 t g h t a 4 t g l t a 4 t g h b 1 b 0 b 3 b 2 b 5 b 4 b 7 b 6 n o t e : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . w h e n t a i i n i s s e l e c t e d , t a i o u t a s s i g n e d o n s a m e p i n c a n n o t b e u s e d . ( i = 0 t o 4 ) t a 1 o s t a 2 o s t a 0 o s o n e - s h o t s t a r t f l a g s y m b o la d d r e s sw h e n r e s e t o n s f0 3 8 2 1 6 0 0 x 0 0 0 0 0 2 t i m e r a 0 o n e - s h o t s t a r t f l a g t i m e r a 1 o n e - s h o t s t a r t f l a g t i m e r a 2 o n e - s h o t s t a r t f l a g t i m e r a 3 o n e - s h o t s t a r t f l a g t i m e r a 4 o n e - s h o t s t a r t f l a g t a 3 o s t a 4 o s b i t n a m ef u n c t i o n b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 n o t h i n g i s a s s i g n e d . t h i s b i t c a n n e i t h e r b e s e t n o r r e s e t . w h e n r e a d , t h e c o n t e n t i s i n d e t e r m i n a t e . t a 0 t g l t a 0 t g h 0 0 : i n p u t o n t a 0 i n i s s e l e c t e d ( n o t e ) 0 1 : t b 2 o v e r f l o w i s s e l e c t e d 1 0 : t a 4 o v e r f l o w i s s e l e c t e d 1 1 : t a 1 o v e r f l o w i s s e l e c t e d t i m e r a 0 e v e n t / t r i g g e r s e l e c t b i t b 7 b 6 n o t e : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . w h e n t a i i n i s s e l e c t e d , t a i o u t a s s i g n e d o n s a m e p i n c a n n o t b e u s e d . ( i = 0 t o 4 ) w r 1 : t i m e r s t a r t w h e n r e a d , t h e v a l u e i s 0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 74 item specification count source f 1 , f 8 , f 32 , f c32 count operation ? down count ? when the timer underflows, it reloads the reload register contents before continuing countin g divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing when the timer underflows tai in pin function programmable i/o port or gate input tai out pin function programmable i/o port or pulse output read from timer count value can be read out by reading timer ai register write to timer ? when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ? gate function counting can be started and stopped by the tai in pins input signal ? pulse output function each time the timer underflows, the tai out pins polarity is reversed (1) timer mode in this mode, the timer counts an internally generated count source. (see table fb-1.) figure fb-6 shows the timer ai mode register in timer mode. table fb-1. specifications of timer mode n o t e 1 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . n o t e 2 : t h e b i t c a n b e 0 o r 1 . n o t e 3 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . t i m e r a i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 t o 4 )0 3 9 6 1 6 t o 0 3 9 a 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 0 : t i m e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a i o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 1 ) ( t a i o u t p i n i s a p u l s e o u t p u t p i n ) g a t e f u n c t i o n s e l e c t b i t 0 x ( n o t e 2 ) : g a t e f u n c t i o n n o t a v a i l a b l e ( t a i i n p i n i s a n o r m a l p o r t p i n ) 1 0 : t i m e r c o u n t s o n l y w h e n t a i i n p i n i s h e l d l ( n o t e 3 ) 1 1 : t i m e r c o u n t s o n l y w h e n t a i i n p i n i s h e l d h ( n o t e 3 ) b 4 b 3 m r 2 m r 1 m r 3 0 ( m u s t a l w a y s b e f i x e d t o 0 i n t i m e r m o d e ) 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 b 7 b 6 t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t 00 0 figure fb-6. timer ai mode register in timer mode
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 75 (2) event counter mode in this mode, the timer counts an external signal or an internal timers overflow. timers a0 and a1 can count a single-phase external signal. timers a2, a3, and a4 can count a single-phase and a two-phase external signal. table fb-2 lists timer specifications when counting a single-phase external signal. fig- ure fb-7 shows the timer ai mode register in event counter mode. table fb-3 lists timer specifications when counting a two-phase external signal. figure fb-8 shows the timer ai mode register in event counter mode. table fb-2. timer specifications in event counter mode (when not processing two-phase pulse signal) item specification count source ?external signals input to tai in pin (effective edge can be selected by software) ?tb2 overflow, taj overflow count operation ?up count or down count can be selected by external signal or software ? when the timer overflows or underflows, the reload register's content is reloaded and the timer starts over again. (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer overflows or underflows tai in pin function programmable i/o port or count source input tai out pin function programmable i/o port, pulse output, or up/down count select input read from timer count value can be read out by reading timer ai register write to timer ?when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ?when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) select function ?free-run count function even when the timer overflows or underflows, the reload register content is not reloaded to it ?pulse output function each time the timer overflows or underflows, the tai out pins polarity is reversed note: this does not apply when the free-run function is selected. b i t n a m ef u n c t i o n t i m e r a i m o d e r e g i s t e r n o t e 1 : i n e v e n t c o u n t e r m o d e , t h e c o u n t s o u r c e i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) . n o t e 2 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . n o t e 3 : v a l i d o n l y w h e n c o u n t i n g a n e x t e r n a l s i g n a l . n o t e 4 : w h e n a n l s i g n a l i s i n p u t t o t h e t a i o u t p i n , t h e d o w n c o u n t i s a c t i v a t e d . w h e n h , t h e u p c o u n t i s a c t i v a t e d . s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 , 1 )0 3 9 6 1 6 , 0 3 9 7 1 6 0 0 1 6 w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e ( n o t e 1 ) b 1 b 0 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a i o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 2 ) ( t a i o u t p i n i s a p u l s e o u t p u t p i n ) c o u n t p o l a r i t y s e l e c t b i t ( n o t e 3 ) m r 2 m r 1 m r 3 0 ( m u s t a l w a y s b e f i x e d t o 0 i n e v e n t c o u n t e r m o d e ) t c k 0 c o u n t o p e r a t i o n t y p e s e l e c t b i t 01 0 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e 1 : c o u n t s e x t e r n a l s i g n a l ' s r i s i n g e d g e u p / d o w n s w i t c h i n g c a u s e s e l e c t b i t 0 : u p / d o w n f l a g ' s c o n t e n t 1 : t a i o u t p i n ' s i n p u t s i g n a l ( n o t e 4 ) 0 : r e l o a d t y p e 1 : f r e e - r u n t y p e b i t s y m b o l t c k 1 i n v a l i d i n e v e n t c o u n t e r m o d e c a n b e 0 o r 1 t m o d 1 figure fb-7. timer ai mode register in event counter mode
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 76 item specification count source ?two-phase pulse signals input to tai in or tai out pin count operation ?up count or down count can be selected by two-phase pulse signal ?when the timer overflows or underflows, the reload register content is reloaded and the timer starts over again (note) divide ratio 1/ (ffff 16 - n + 1) for up count 1/ (n + 1) for down count n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing timer overflows or underflows tai in pin function two-phase pulse input tai out pin function two-phase pulse input read from timer count value can be read out by reading timer a2, a3, or a4 register write to timer ?when counting stopped when a value is written to timer a2, a3, or a4 register, it is written to both reload register and counter ?when counting in progress when a value is written to timer a2, a3, or a4 register, it is written to only reload register. (transferred to counter at next reload time.) select function ?normal processing operation the timer counts up rising edges or counts down falling edges on the tai in pin when input signal on the tai out pin is h ?multiply-by-4 processing operation if the phase relationship is such that the tai in pin goes h when the input signal on the tai out pin is h, the timer counts up rising and falling edges on the tai out and tai in pins. if the phase relationship is such that the tai in pin goes l when the input signal on the tai out pin is h, the timer counts down rising and falling edges on the tai out and tai in pins. note: this does not apply when the free-run function is selected. table fb-3. timer specifications in event counter mode (when processing two-phase pulse signal with timer a2,a3 and a4 tai out up count up count up count down count down count down count tai in (i=2,3) tai out tai in (i=3,4) count up all edges count up all ed g es count down all edges count down all ed g es
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 77 b i t s y m b o lb i t n a m ef u n c t i o n b i t n a m ef u n c t i o n n o t e 1 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d n o t e 2 : t h i s b i t i s v a l i d w h e n o n l y c o u n t i n g a n e x t e r n a l s i g n a l . n o t e 3 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . n o t e 4 : t h i s b i t i s v a l i d f o r t i m e r a 3 m o d e r e g i s t e r . f o r t i m e r a 2 a n d a 4 m o d e r e g i s t e r s , t h i s b i t c a n b e 0 o r 1 . n o t e 5 : w h e n p e r f o r m i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g , m a k e s u r e t h e t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g o p e r a t i o n s e l e c t b i t ( a d d r e s s 0 3 8 4 1 6 ) i s s e t t o 1 . a l s o , a l w a y s b e s u r e t o s e t t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) t o 0 0 . t i m e r a i m o d e r e g i s t e r ( w h e n n o t u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 2 t o 4 )0 3 9 8 1 6 t o 0 3 9 a 1 6 0 0 1 6 b i t s y m b o l b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a i o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 1 ) ( t a i o u t p i n i s a p u l s e o u t p u t p i n ) c o u n t p o l a r i t y s e l e c t b i t ( n o t e 2 ) m r 2 m r 1 m r 3 0 ( m u s t a l w a y s b e 0 i n e v e n t c o u n t e r m o d e ) t c k 1 t c k 0 01 0 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e s 1 : c o u n t s e x t e r n a l s i g n a l ' s r i s i n g e d g e s u p / d o w n s w i t c h i n g c a u s e s e l e c t b i t 0 : u p / d o w n f l a g ' s c o n t e n t 1 : t a i o u t p i n ' s i n p u t s i g n a l ( n o t e 3 ) w r c o u n t o p e r a t i o n t y p e s e l e c t b i t t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g o p e r a t i o n s e l e c t b i t ( n o t e 4 ) ( n o t e 5 ) 0 : r e l o a d t y p e 1 : f r e e - r u n t y p e 0 : n o r m a l p r o c e s s i n g o p e r a t i o n 1 : m u l t i p l y - b y - 4 p r o c e s s i n g o p e r a t i o n n o t e 1 : t h i s b i t i s v a l i d f o r t i m e r a 3 m o d e r e g i s t e r . f o r t i m e r a 2 a n d a 4 m o d e r e g i s t e r s , t h i s b i t c a n b e 0 o r 1 . n o t e 2 : w h e n p e r f o r m i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g , m a k e s u r e t h e t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g o p e r a t i o n s e l e c t b i t ( a d d r e s s 0 3 8 4 1 6 ) i s s e t t o 1 . a l s o , a l w a y s b e s u r e t o s e t t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) t o 0 0 . t i m e r a i m o d e r e g i s t e r ( w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 2 t o 4 )0 3 9 8 1 6 t o 0 3 9 a 1 6 0 0 1 6 b 7b 6 b 5b 4b 3 b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 0 ( m u s t a l w a y s b e 0 w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) 0 ( m u s t a l w a y s b e 0 w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) m r 2 m r 1 m r 3 0 ( m u s t a l w a y s b e 0 w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) t c k 1 t c k 0 01 0 1 ( m u s t a l w a y s b e 1 w h e n u s i n g t w o - p h a s e p u l s e s i g n a l p r o c e s s i n g ) w r c o u n t o p e r a t i o n t y p e s e l e c t b i t t w o - p h a s e p u l s e p r o c e s s i n g o p e r a t i o n s e l e c t b i t ( n o t e 1 ) ( n o t e 2 ) 0 : r e l o a d t y p e 1 : f r e e - r u n t y p e 0 : n o r m a l p r o c e s s i n g o p e r a t i o n 1 : m u l t i p l y - b y - 4 p r o c e s s i n g o p e r a t i o n 0 0 1 figure fb-8. timer ai mode register in event counter m
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 78 item specification count source f1, f 8 , f 32 , f c32 count operation ? the timer counts down ? when the count reaches 0000 16 , the timer stops counting after reloading a new count ? if a trigger occurs when counting, the timer reloads a new count and restarts counting divide ratio 1/n n : set value count start condition ? an external trigger is input ? the timer overflows ? the one-shot start flag is set (= 1) count stop condition ? a new count is reloaded after the count has reached 0000 16 ? the count start flag is reset (= 0) interrupt request generation timing the count reaches 0000 16 tai in pin function programmable i/o port or trigger input tai out pin function programmable i/o port or pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ?when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ? when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) (3) one-shot timer mode in this mode, the timer operates only once. (see table fb-4.) when a trigger occurs, the timer starts up and continues operating for a given period. figure fb-9 shows the timer ai mode register in one-shot timer mode. table fb-4. timer specifications in one-shot timer mode figure fb-9. timer ai mode register in one-shot timer mode b i t n a m ef u n c t i o n b i t s y m b o l t i m e r a i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 t o 4 )0 3 9 6 1 6 t o 0 3 9 a 1 6 0 0 1 6 b 7b 6b 5 b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 1 0 : o n e - s h o t t i m e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 p u l s e o u t p u t f u n c t i o n s e l e c t b i t 0 : p u l s e i s n o t o u t p u t ( t a i o u t p i n i s a n o r m a l p o r t p i n ) 1 : p u l s e i s o u t p u t ( n o t e 1 ) ( t a i o u t p i n i s a p u l s e o u t p u t p i n ) m r 2 m r 1 w r m r 3 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 b 7 b 6 t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t 10 0 0 : o n e - s h o t s t a r t f l a g i s v a l i d 1 : s e l e c t e d b y e v e n t / t r i g g e r s e l e c t r e g i s t e r t r i g g e r s e l e c t b i t e x t e r n a l t r i g g e r s e l e c t b i t ( n o t e 2 ) 0 : f a l l i n g e d g e o f t a i i n p i n ' s i n p u t s i g n a l ( n o t e 3 ) 1 : r i s i n g e d g e o f t a i i n p i n ' s i n p u t s i g n a l ( n o t e 3 ) n o t e 1 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d n o t e 2 : v a l i d o n l y w h e n t h e t a i i n p i n i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) . i f t i m e r o v e r f l o w i s s e l e c t e d , t h i s b i t c a n b e 1 o r 0 . n o t e 3 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . 0 ( m u s t a l w a y s b e 0 i n o n e - s h o t t i m e r m o d e )
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 79 (4) pulse width modulation (pwm) mode in this mode, the timer outputs pulses of a given width in succession. (see table fb-5.) in this mode, the counter functions as either a 16-bit pulse width modulator or an 8-bit pulse width modulator. figure fb-10 shows the timer ai mode register in pulse width modulation mode. figure fb-11 shows the example of how a 16-bit pulse width modulator operates. figure fb-12 shows the example of how an 8-bit pulse width modulator operates. table fb-5. timer specifications in pulse width modulation mode figure fb-10. timer ai mode register in pulse width modulation mode item specification count source f 1 , f 8 , f 32 , f c32 count operation ? the timer counts down (operating as an 8-bit or a 16-bit pulse width modulator) ? the timer reloads a new count at a rising edge of pwm pulse and continues counting ?the timer is not affected by a trigger that occurs when counting 16-bit pwm ?high level width n / fi n : set value ?cycle time (2 16 -1) / fi fixed 8-bit pwm ?high level width n x (m+1) / fi n : values set to timer ai registers high-order address ?cycle time (2 8 -1) x (m+1) / fi m : values set to timer ai registers low-order address count start condition ?external trigger is input ?the timer overflows ?the count start flag is set (= 1) count stop condition ?the count start flag is reset (= 0) interrupt request generation timing pwm pulse goes l tai in pin function programmable i/o port or trigger input tai out pin function pulse output read from timer when timer ai register is read, it indicates an indeterminate value write to timer ?when counting stopped when a value is written to timer ai register, it is written to both reload register and counter ?when counting in progress when a value is written to timer ai register, it is written to only reload register (transferred to counter at next reload time) t i m e r a i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t a i m r ( i = 0 t o 4 )0 3 9 6 1 6 t o 0 3 9 a 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l b 7 b 6b 5b 4b 3 b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 1 1 : p w m m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 m r 2 m r 1 m r 3 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 b 7 b 6 t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t w r 11 1 1 ( m u s t a l w a y s b e f i x e d t o 1 i n p w m m o d e ) 1 6 / 8 - b i t p w m m o d e s e l e c t b i t 0 : f u n c t i o n s a s a 1 6 - b i t p u l s e w i d t h m o d u l a t o r 1 : f u n c t i o n s a s a n 8 - b i t p u l s e w i d t h m o d u l a t o r t r i g g e r s e l e c t b i t e x t e r n a l t r i g g e r s e l e c t b i t ( n o t e 1 ) 0 : f a l l i n g e d g e o f t a i i n p i n ' s i n p u t s i g n a l ( n o t e 2 ) 1 : r i s i n g e d g e o f t a i i n p i n ' s i n p u t s i g n a l ( n o t e 2 ) 0 : c o u n t s t a r t f l a g i s v a l i d 1 : s e l e c t e d b y e v e n t / t r i g g e r s e l e c t r e g i s t e r n o t e 1 : v a l i d o n l y w h e n t h e t a i i n p i n i s s e l e c t e d b y t h e e v e n t / t r i g g e r s e l e c t b i t ( a d d r e s s e s 0 3 8 2 1 6 a n d 0 3 8 3 1 6 ) . i f t i m e r o v e r f l o w i s s e l e c t e d , t h i s b i t c a n b e 1 o r 0 n o t e 2 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 .
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer a 80 figure fb-11. example of how a 16-bit pulse width modulator operates figure fb-12. example of how an 8-bit pulse width modulator operates f i : frequency of count source (f 1 , f 8 , f 32 , f c32 ) trigger is not generated by this signal count source condition : reload register = 0003 16 , when external trigger (falling edge of ta0 in pin's input signal) is selected. 1 / f i x (2 ?) 16 ta0 in pin's input signal pwm pulse output from ta0 out pin ? ? ? ? timer a0 interrupt request bit ? ? cleared to ??by software, or when interrupt request is accepted. note: n = 0000 16 to fffe 16 . 1 / f i x n c o u n t s o u r c e ( n o t e 1 ) t a 0 i n p i n ' s i n p u t s i g n a l u n d e r f l o w s i g n a l o f 8 - b i t p r e s c a l e r ( n o t e 2 ) p w m p u l s e o u t p u t f r o m t a 0 o u t p i n h h l l t i m e r a 0 i n t e r r u p t r e q u e s t b i t f i : f r e q u e n c y o f c o u n t s o u r c e ( f 1 , f 8 , f 3 2 , f c 3 2 ) n o t e 1 : t h e 8 - b i t p r e s c a l e r c o u n t s t h e c o u n t s o u r c e . n o t e 2 : t h e 8 - b i t p u l s e w i d t h m o d u l a t o r c o u n t s t h e 8 - b i t p r e s c a l e r ' s u n d e r f l o w s i g n a l . n o t e 3 : m = 0 0 1 6 t o f e 1 6 ; n = 0 0 1 6 t o f e 1 6 . c o n d i t i o n : r e l o a d r e g i s t e r ' s h i g h - o r d e r 8 b i t s = 0 2 1 6 r e l o a d r e g i s t e r ' s l o w - o r d e r b i t s 8 = 0 2 1 6 w h e n e x t e r n a l t r i g g e r ( f a l l i n g e d g e o f t a 0 i n p i n ' s i n p u t s i g n a l ) i s s e l e c t e d . 1 / f i x ( m + 1 ) x ( 2 1 ) 8 1 / f i x ( m + 1 ) x n 1 / f i x ( m + 1 ) c l e a r e d t o 0 b y s o f t w a r e , o r w h e n i n t e r r u p t r e q u e s t i s a c c e p t e d . h l 1 0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer b 81 timer b figure ta-1 shows the block diagram of timer b. figures ta-2 and ta-3 show the timer b-related registers. use the timer bi mode register (i = 0 to 2) bits 0 and 1 to choose the desired mode. timer b has three operation modes listed as follows: ? timer mode: the timer counts an internal count source. ? event counter mode: the timer counts pulses from an external source or a timer overflow. ? pulse period/pulse width measuring mode: the timer measures an external signal's pulse period or pulse width. figure ta-1. block diagram of timer b clock source selection (address 0380 16 ) ?event counter ?timer ?pulse period/pulse width measurement reload register (16) low-order 8 bits high-order 8 bits data bus low-order bits data bus high-order bits f 1 f 8 f 32 tbj overflow (j = i - 1. note, however, j = 2 when i = 0) can be selected in only event counter mode count start flag fc 32 polarity switching and edge pulse (i = 0 to 2) counter reset circuit counter (16) tbi address tbj timer b0 0391 16 0390 16 timer b2 timer b1 0393 16 0392 16 timer b0 timer b2 0395 16 0394 16 timer b1 tbi in t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t s y m b o l b i t n a m e f u n c t i o n w r b 7b 6b 5b 4b 3b 2b 1b 0 0 0 : t i m e r m o d e 0 1 : e v e n t c o u n t e r m o d e 1 0 : p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e 1 1 : i n h i b i t e d b 1 b 0 t c k 1 m r 3 m r 2 m r 1 t m o d 1 m r 0 t m o d 0 t c k 0 f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e c o u n t s o u r c e s e l e c t b i t ( f u n c t i o n v a r i e s w i t h e a c h o p e r a t i o n m o d e ) o p e r a t i o n m o d e s e l e c t b i t ( n o t e 1 ) ( n o t e 2 ) n o t e 1 : t i m e r b 0 . n o t e 2 : t i m e r b 1 , t i m e r b 2 . figure ta-2. timer b-related registers (1)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer b 82 figure ta-3. timer b-related registers (2) s y m b o la d d r e s sw h e n r e s e t t a b s r0 3 8 0 1 6 0 0 1 6 c o u n t s t a r t f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 t i m e r b 2 c o u n t s t a r t f l a g t i m e r b 1 c o u n t s t a r t f l a g t i m e r b 0 c o u n t s t a r t f l a g t i m e r a 4 c o u n t s t a r t f l a g t i m e r a 3 c o u n t s t a r t f l a g t i m e r a 2 c o u n t s t a r t f l a g t i m e r a 1 c o u n t s t a r t f l a g t i m e r a 0 c o u n t s t a r t f l a g 0 : s t o p s c o u n t i n g 1 : s t a r t s c o u n t i n g t b 2 s t b 1 s t b 0 s t a 4 s t a 3 s t a 2 s t a 1 s t a 0 s s y m b o la d d r e s sw h e n r e s e t c p s r f0 3 8 1 1 6 0 x x x x x x x 2 c l o c k p r e s c a l e r r e s e t f l a g b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 c l o c k p r e s c a l e r r e s e t f l a g 0 : n o e f f e c t 1 : p r e s c a l e r i s r e s e t ( w h e n r e a d , t h e v a l u e i s 0 ) c p s r s y m b o la d d r e s sw h e n r e s e t t b 00 3 9 1 1 6 , 0 3 9 0 1 6 i n d e t e r m i n a t e t b 10 3 9 3 1 6 , 0 3 9 2 1 6 i n d e t e r m i n a t e t b 20 3 9 5 1 6 , 0 3 9 4 1 6 i n d e t e r m i n a t e b 7b 0b 7b 0 ( b 1 5 )( b 8 ) t i m e r b i r e g i s t e r ( n o t e ) w r p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e m e a s u r e s a p u l s e p e r i o d o r w i d t h t i m e r m o d e0 0 0 0 1 6 t o f f f f 1 6 c o u n t s t h e t i m e r ' s p e r i o d f u n c t i o n v a l u e s t h a t c a n b e s e t e v e n t c o u n t e r m o d e0 0 0 0 1 6 t o f f f f 1 6 c o u n t s e x t e r n a l p u l s e s i n p u t o r a t i m e r o v e r f l o w n o t e : r e a d a n d w r i t e d a t a i n 1 6 - b i t u n i t s . n o t h i n g i s a s s i g n e d . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e .
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer b 83 item specification count source f 1 , f 8 , f 32 , f c32 count operation ?counts down ?when the timer underflows, the reload register's content is reloaded and the timer starts over again. divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing the timer underflows tbi in pin function programmable i/o port read from timer count value is read out by reading timer bi register write to timer ?when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ? when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) (1) timer mode in this mode, the timer counts an internally generated count source. (see table ta-1.) figure ta-4 shows the timer bi mode register in timer mode. table ta-1. timer specifications in timer mode figure ta-4. timer bi mode register in timer mode n o t e 1 : t i m e r b 0 . n o t e 2 : t i m e r b 1 , t i m e r b 2 . t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 0 : t i m e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 i n v a l i d i n t i m e r m o d e c a n b e 0 o r 1 m r 2 m r 1 m r 3 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 t c k 1 t c k 0 c o u n t s o u r c e s e l e c t b i t 0 i n v a l i d i n t i m e r m o d e . i n a n a t t e m p t t o w r i t e t o t h e s e b i t s , w r i t e 0 . t h e v a l u e , i f r e a d i n t i m e r m o d e , t u r n s o u t t o b e i n d e t e r m i n a t e . 0 0 ( f i x e d t o 0 i n t i m e r m o d e ; i = 0 ) n o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . ( n o t e 1 ) ( n o t e 2 ) b 7 b 6
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer b 84 figure ta-5. timer bi mode register in event counter mode (2) event counter mode in this mode, the timer counts an external signal or an internal timer's overflow. (see table ta-2.) figure ta-5 shows the timer bi mode register in event counter mode. table ta-2. timer specifications in event counter mode item specification count source ?external signals input to tbi in pin ?effective edge of count source can be a rising edge, a falling edge, or falling and rising edges as selected by software count operation ?counts down ?when the timer underflows, it reloads the reload register contents before continuing counting divide ratio 1/(n+1) n : set value count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) i nterrupt request generation timing the timer underflows tbi in pin function count source input read from timer count value can be read out by reading timer bi register write to timer ?when counting stopped when a value is written to timer bi register, it is written to both reload register and counter ?when counting in progress when a value is written to timer bi register, it is written to only reload register (transferred to counter at next reload time) t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t n a m ef u n c t i o n b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 0 1 : e v e n t c o u n t e r m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0c o u n t p o l a r i t y s e l e c t b i t ( n o t e 1 ) m r 2 m r 1 m r 3 i n v a l i d i n e v e n t c o u n t e r m o d e . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d i n e v e n t c o u n t e r m o d e , t u r n s o u t t o b e i n d e t e r m i n a t e . t c k 1 t c k 0 01 0 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g e d g e s 0 1 : c o u n t s e x t e r n a l s i g n a l ' s r i s i n g e d g e s 1 0 : c o u n t s e x t e r n a l s i g n a l ' s f a l l i n g a n d r i s i n g e d g e s 1 1 : i n h i b i t e d b 3 b 2 n o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d , t u r n s o u t t o b e i n d e t e r m i n a t e . n o t e 1 : v a l i d o n l y w h e n i n p u t f r o m t h e t b i i n p i n i s s e l e c t e d a s t h e e v e n t c l o c k . i f t i m e r ' s o v e r f l o w i s s e l e c t e d , t h i s b i t c a n b e 0 o r 1 . n o t e 2 : t i m e r b 0 . n o t e 3 : t i m e r b 1 , t i m e r b 2 . n o t e 4 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . i n v a l i d i n e v e n t c o u n t e r m o d e . c a n b e 0 o r 1 . e v e n t c l o c k s e l e c t 0 : i n p u t f r o m t b i i n p i n ( n o t e 4 ) 1 : t b j o v e r f l o w ( j = i - 1 ; h o w e v e r , j = 2 w h e n i = 0 ) 0 ( f i x e d t o 0 i n e v e n t c o u n t e r m o d e ; i = 0 ) ( n o t e 2 ) ( n o t e 3 )
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer b 85 item specification count source f 1 , f 8 , f 32 , f c32 count operation ?up count ?counter value 0000 16 is transferred to reload register at measurement pulse's effective edge and the timer continues counting count start condition count start flag is set (= 1) count stop condition count start flag is reset (= 0) interrupt request generation timing ?when measurement pulse's effective edge is input (note 1) ?when an overflow occurs. (simultaneously, the timer bi overflow flag changes to 1. the timer bi overflow flag changes to 0 when the count start flag is 1 and a value is written to the timer bi mode register.) tbi in pin function measurement pulse input read from timer when timer bi register is read, it indicates the reload registers content (measurement result) (note 2) write to timer cannot be written to note 1: an interrupt request is not generated when the first effective edge is input after the timer has started counting. note 2: the value read out from the timer bi register is indeterminate until the second effective edge is input after the timer. (3) pulse period/pulse width measurement mode in this mode, the timer measures the pulse period or pulse width of an external signal. (see table ta-3.) figure ta-6 shows the timer bi mode register in pulse period/pulse width measurement mode. figure ta-7 shows the operation timing when measuring a pulse period. figure ta-8 shows the operation timing when measuring a pulse width. table ta-3. timer specifications in pulse period/pulse width measurement mode figure ta-6. timer bi mode register in pulse period/pulse width measurement mode t i m e r b i m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t t b i m r ( i = 0 t o 2 )0 3 9 b 1 6 t o 0 3 9 d 1 6 0 0 x x 0 0 0 0 2 b i t n a m e b i t s y m b o l w r b 7b 6b 5b 4b 3b 2b 1b 0 o p e r a t i o n m o d e s e l e c t b i t 1 0 : p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e b 1 b 0 t m o d 1 t m o d 0 m r 0 m e a s u r e m e n t m o d e s e l e c t b i t m r 2 m r 1 m r 3 t c k 1 t c k 0 0 1 0 0 : p u l s e p e r i o d m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s f a l l i n g e d g e t o f a l l i n g e d g e ) 0 1 : p u l s e p e r i o d m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s r i s i n g e d g e t o r i s i n g e d g e ) 1 0 : p u l s e w i d t h m e a s u r e m e n t ( i n t e r v a l b e t w e e n m e a s u r e m e n t p u l s e ' s f a l l i n g e d g e t o r i s i n g e d g e , a n d b e t w e e n r i s i n g e d g e t o f a l l i n g e d g e ) 1 1 : i n h i b i t e d f u n c t i o n b 3 b 2 n o t h i n g i s a s s i g n e d ( i = 1 , 2 ) . i n a n a t t e m p t t o w r i t e t o t h i s b i t , w r i t e 0 . t h e v a l u e , i f r e a d i n e v e n t c o u n t e r m o d e , t u r n s o u t t o b e i n d e t e r m i n a t e . c o u n t s o u r c e s e l e c t b i t t i m e r b i o v e r f l o w f l a g ( n o t e 1 ) 0 : t i m e r d i d n o t o v e r f l o w 1 : t i m e r h a s o v e r f l o w e d 0 0 : f 1 0 1 : f 8 1 0 : f 3 2 1 1 : f c 3 2 b 7 b 6 n o t e 1 : t h e t i m e r b i o v e r f l o w f l a g c h a n g e s t o 0 w h e n t h e c o u n t s t a r t f l a g i s 1 a n d a v a l u e i s w r i t t e n t o t h e t i m e r b i m o d e r e g i s t e r . t h i s f l a g c a n n o t b e s e t t o 1 b y s o f t w a r e . n o t e 2 : t i m e r b 0 . n o t e 3 : t i m e r b 1 , t i m e r b 2 . 0 ( f i x e d t o 0 i n p u l s e p e r i o d / p u l s e w i d t h m e a s u r e m e n t m o d e ; i = 0 ) ( n o t e 2 ) ( n o t e 3 )
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timer b 86 figure ta-8. operation timing when measuring a pulse width figure ta-7. operation timing when measuring a pulse period count source measurement pulse count start flag timer bi interrupt request bit timing when counter reaches ?000 16 ? ? transfer (indeterminate value) reload register counter transfer timing ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) measurement of puls time interval from falling edge to falling edge (note 2) cleared to ??by software, or when interrupt request is accepted. transfer (measured value) ? measurement pulse ? count source reload register counter transfer timing count start flag timer bi interrupt request bit timing when counter reaches 0000 16 ? ? ? ? ? timer bi overflow flag ? ? note 1: counter is initialized at completion of measurement. note 2: timer has overflowed. (note 1) (note 1) (note 1) (note 1) cleared to ??by software, or when interrupt request is accepted. (note 2) transfer (measured value) transfer (indeterminate value)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o 87 figure ga-1. block diagram of uarti (i = 0, 1) serial i/o serial i/o is configured as two channels: uart0 and uart1. uart0 and uart1 each have an exclusive timer to generate a transfer clock, so they operate independently of each other. figure ga-1 shows the block diagram of uart0 and uart1. figures ga-2 shows the block diagram of the transmit/receive unit. uarti (i=0, 1) has two operation modes: a clock synchronous serial i/o mode and a clock asynchronous serial i/o mode (uart mode). the contents of the serial i/o mode select bits (bits 0 to 2 at addresses 03a0 16 and 03a8 16 ) determine whether uarti is used as a clock synchronous serial i/o or as a uart. although a few function are different, uart0 and uart1 have almost same functions. figures ga-3 through ga-5 show the registers related to uarti. m: values set to uart0 bit rate generator (u0brg) n : values set to u art1 bit rate g enerator (u 1br g) rxd 0 1 / (m+1) 1/16 1/16 1/2 bit rate generator (address 03a1 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 0 clock source selection cts 0 / rts 0 f 1 f 8 f 32 internal external vcc rts0 cts0 txd 0 transmit/ receive unit rxd 1 1 / (n+1) 1/16 1/16 1/2 bit rate generator (address 03a9 16 ) clock synchronous type (when internal clock is selected) uart reception clock synchronous type uart transmission clock synchronous type clock synchronous type (when internal clock is selected) clock synchronous type (when external clock is selected) receive clock transmit clock clk 1 clock source selection f 1 f 8 f 32 internal external rts 1 cts 1 txd 1 (uart1) (uart0) polarity reversing circuit polarity reversing circuit cts/rts disabled clock output pin select switch cts 1 / rts 1 clks 1 cts/rts disabled cts/rts selected cts/rts disabled v cc cts/rts disabled reception control circuit transmission control circuit reception control circuit transmission control circuit transmit/ receive unit
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o 88 figure ga-2. block diagram of transmit/receive unit sp sp par 2sp 1sp uart uart (7 bits) uart (8 bits) uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type txdi uarti transmit register par enabled par disabled d 8 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 sp: stop bit par: parity bit uarti transmit buffer register msb/lsb conversion circuit uart (8 bits) uart (9 bits) clock synchronouss type uarti receive buffer register uarti receive register 2sp 1sp par enabled par disabled uart uart (7 bits) uart (9 bits) clock synchronous type clock synchronous type uart (7 bits) uart (8 bits) rxdi clock synchronous type uart (8 bits) uart (9 bits) address 03a6 16 address 03a7 16 address 03ae 16 address 03af 16 address 03a2 16 address 03a3 16 address 03aa 16 address 03ab 16 data bus low-order bits msb/lsb conversion circuit 0000000 sp sp par "0" data bus high-order bits d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 8
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o 89 figure ga-3. serial i/o-related registers (1) b7 b0 (b15) (b8) b7 b0 uarti transmit buffer register function transmission data symbol address when reset u0tb 03a3 16 , 03a2 16 indeterminate u1tb 03ab 16 , 03aa 16 indeterminate uarti bit rate generator b7 b0 symbol address when reset u0brg 03a1 16 indeterminate u1brg 03a9 16 indeterminate function assuming that set value = n, brgi divides the count source by (n + 1) 00 16 to ff 16 values that can be set symbol address when reset u0rb 03a7 16 , 03a6 16 indeterminate u1rb 03af 16 , 03ae 16 indeterminate b7 b0 (b15) (b8) b7 b0 uarti receive buffer register function (during uart mode) function (during clock synchronous serial i/o mode) bit name bit symbol 0 : no framing error 1 : framing error found 0 : no parity error 1 : parity error found 0 : no error 1 : error found note: bits 15 through 12 are set to ??when the serial i/o mode select bit (bits 2 to 0 at addresses 03a0 16 and 03a8 16 ) are set to ?00 2 ?or the receive enable bit is set to ?? (bit 15 is set to ??when bits 14 to 12 all are set to ??) bits 14 and 13 are also set to ??when the lower byte of the uarti receive buffer register (addresses 03a6 16 and 03ae 16 ) is read out. invalid invalid invalid oer fer per sum overrun error flag (note) framing error flag (note) parity error flag (note) error sum flag (note) 0 : no overrun error 1 : overrun error found 0 : no overrun error 1 : overrun error found reception data w r w r w r reception data nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ??
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o 90 figure ga-4. serial i/o-related registers (2) w r u a r t i t r a n s m i t / r e c e i v e m o d e r e g i s t e r s y m b o la d d r e s sw h e n r e s e t u i m r ( i = 0 , 1 )0 3 a 0 1 6 , 0 3 a 8 1 6 0 0 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 b i t n a m e b i t s y m b o l m u s t b e f i x e d t o 0 0 1 0 0 0 : s e r i a l i / o i n v a l i d 0 1 0 : i n h i b i t e d 0 1 1 : i n h i b i t e d 1 1 1 : i n h i b i t e d b 2 b 1 b 0 c k d i r s m d 1 s m d 0 s e r i a l i / o m o d e s e l e c t b i t s m d 2 i n t e r n a l / e x t e r n a l c l o c k s e l e c t b i t s t p s p r y p r y e s l e p p a r i t y e n a b l e b i t 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k s t o p b i t l e n g t h s e l e c t b i t o d d / e v e n p a r i t y s e l e c t b i t s l e e p s e l e c t b i t 0 : o n e s t o p b i t 1 : t w o s t o p b i t s 0 : p a r i t y d i s a b l e d 1 : p a r i t y e n a b l e d 0 : s l e e p m o d e d e s e l e c t e d 1 : s l e e p m o d e s e l e c t e d 1 0 0 : t r a n s f e r d a t a 7 b i t s l o n g 1 0 1 : t r a n s f e r d a t a 8 b i t s l o n g 1 1 0 : t r a n s f e r d a t a 9 b i t s l o n g 0 0 0 : s e r i a l i / o i n v a l i d 0 1 0 : i n h i b i t e d 0 1 1 : i n h i b i t e d 1 1 1 : i n h i b i t e d b 2 b 1 b 0 0 : i n t e r n a l c l o c k 1 : e x t e r n a l c l o c k i n v a l i d v a l i d w h e n b i t 6 = 1 0 : o d d p a r i t y 1 : e v e n p a r i t y i n v a l i d i n v a l i d m u s t a l w a y s b e 0 f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) u a r t i t r a n s m i t / r e c e i v e c o n t r o l r e g i s t e r 0 s y m b o la d d r e s sw h e n r e s e t u i c 0 ( i = 0 , 1 )0 3 a 4 1 6 , 0 3 a c 1 6 0 8 1 6 b 7b 6b 5b 4b 3b 2b 1b 0 f u n c t i o n ( d u r i n g u a r t m o d e ) f u n c t i o n ( d u r i n g c l o c k s y n c h r o n o u s s e r i a l i / o m o d e ) t x e p t c l k 1 c l k 0 c r s c r d n c h c k p o l b r g c o u n t s o u r c e s e l e c t b i t t r a n s m i t r e g i s t e r e m p t y f l a g 0 : t r a n s m i t d a t a i s o u t p u t a t f a l l i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t r i s i n g e d g e 1 : t r a n s m i t d a t a i s o u t p u t a t r i s i n g e d g e o f t r a n s f e r c l o c k a n d r e c e i v e d a t a i s i n p u t a t f a l l i n g e d g e c l k p o l a r i t y s e l e c t b i t c t s / r t s f u n c t i o n s e l e c t b i t c t s / r t s d i s a b l e b i t d a t a o u t p u t s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 0 : l s b f i r s t 1 : m s b f i r s t 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) 0 : c t s / r t s f u n c t i o n e n a b l e d 1 : c t s / r t s f u n c t i o n d i s a b l e d ( p 4 7 a n d p 7 7 f u n c t i o n a s p r o g r a m m a b l e i / o p o r t ) 0 : t x d i p i n i s c m o s o u t p u t 1 : t x d i p i n i s n - c h a n n e l o p e n - d r a i n o u t p u t u f o r mt r a n s f e r f o r m a t s e l e c t b i t 0 0 : f 1 i s s e l e c t e d 0 1 : f 8 i s s e l e c t e d 1 0 : f 3 2 i s s e l e c t e d 1 1 : i n h i b i t e d b 1 b 0 v a l i d w h e n b i t 4 = 0 0 : c t s f u n c t i o n i s s e l e c t e d ( n o t e 1 ) 1 : r t s f u n c t i o n i s s e l e c t e d ( n o t e 2 ) v a l i d w h e n b i t 4 = 0 0 : c t s f u n c t i o n i s s e l e c t e d ( n o t e 1 ) 1 : r t s f u n c t i o n i s s e l e c t e d ( n o t e 2 ) 0 : d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( d u r i n g t r a n s m i s s i o n ) 1 : n o d a t a p r e s e n t i n t r a n s m i t r e g i s t e r ( t r a n s m i s s i o n c o m p l e t e d ) 0 : t x d i p i n i s c m o s o u t p u t 1 : t x d i p i n i s n - c h a n n e l o p e n - d r a i n o u t p u t m u s t a l w a y s b e 0 b i t n a m e b i t s y m b o l m u s t a l w a y s b e 0 n o t e 1 : s e t t h e c o r r e s p o n d i n g p o r t d i r e c t i o n r e g i s t e r t o 0 . n o t e 2 : t h e s e t t i n g s o f t h e c o r r e s p o n d i n g p o r t r e g i s t e r a n d p o r t d i r e c t i o n r e g i s t e r a r e i n v a l i d . 0 : c t s / r t s f u n c t i o n e n a b l e d 1 : c t s / r t s f u n c t i o n d i s a b l e d ( p 4 7 a n d p 7 7 f u n c t i o n a s p r o g r a m m a b l e i / o p o r t ) w r
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o 91 figure ga-5. serial i/o-related registers (3) uarti transmit/receive control register 1 symbol address when reset uic1(i=0,1) 03a5 16 , 03ad 16 02 16 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) te ti re ri transmit enable bit receive enable bit receive complete flag transmit buffer empty flag 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : transmission disabled 1 : transmission enabled 0 : data present in transmit buffer register 1 : no data present in transmit buffer register 0 : reception disabled 1 : reception enabled 0 : no data present in receive buffer register 1 : data present in receive buffer register 0 : no data present in receive buffer register 1 : data present in receive buffer register note: when using multiple pins to output the transfer clock, the following requirement must be met: ?uart1 internal/external clock select bit (bit 3 at address 03a8 16 ) = ?? uart transmit/receive control register 2 symbol address when reset ucon 03b0 16 x0000000 2 b7 b6 b5 b4 b3 b2 b1 b0 bit name bit symbol w r function (during uart mode) function (during clock synchronous serial i/o mode) clkmd0 clkmd1 uart0 transmit interrupt cause select bit uart0 continuous receive mode enable bit 0 : continuous receive mode disabled 1 : continuous receive mode enable uart1 continuous receive mode enable bit clk/clks select bit 0 uart1 transmit interrupt cause select bit 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : normal mode (clk output is clk1 only) 1 : transfer clock output from multiple pins function selected 0 : continuous receive mode disabled 1 : continuous receive mode enabled 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) 0 : transmit buffer empty (tl = 1) 1 : transmission completed (txept = 1) must always be ? u0irs u1irs u0rrm u1rrm invalid invalid invalid clk/clks select bit 1 (note) valid when bit 5 = ?? 0 : clock output to clk1 1 : clock output to clks1 reserved bit must always be ? must always be ? nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be ?? 0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 92 (1) clock synchronous serial i/o mode the clock synchronous serial i/o mode uses a transfer clock to transmit and receive data. table ga-1 lists the specifications of the clock synchronous serial i/o mode. figure ga-6 shows the uarti transmit/ receive mode register. table ga-1. specifications of clock synchronous serial i/o mode specification ? transfer data length: 8 bits ? when internal clock is selected (bit 3 at address 03a0 16 , 03a8 16 = 0) : fi/ 2(n+1) (note 1) fi = f 1 , f 8 , f 32 ? when external clock is selected (bit 3 at address 03a0 16 , 03a8 16 =1) : input from clki pin (note 2) _______ ________ _______ ________ ? cts function/ rts function/ cts,rts function chosen to be invalid ? to start transmission, the following requirements must be met: _ transmit enable bit (bit 0 at address 03a5 16 , 03ad 16 ) = 1 _ transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 ) = 0 _______ _______ _ when cts function is selected, cts input level = "l" ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at address 03a4 16 , 03ac 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at address 03a4 16 , 03ac 16 ) = 1: clki input level = l ? to start reception, the following requirements must be met: _ receive enable bit (bit 2 at address 03a5 16 , 03ad 16 ) = 1 _ transmit enable bit (bit 0 at address 03a5 16 , 03ad 16 ) = 1 _ transmit buffer empty flag (bit 1 at address 03a5 16 , 03ad 16 ) = 0 ? furthermore, if external clock is selected, the following requirements must also be met: _ clki polarity select bit (bit 6 at address 03a4 16 , 03ac 16 ) = 0: clki input level = h _ clki polarity select bit (bit 6 at address 03a4 16 , 03ac 16 ) = 1: clki input level = l ? when transmitting _ transmit interrupt cause select bit (bits 0,1 at address 03b0 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed _ transmit interrupt cause select bit (bits 0,1 at address 03b0 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ? when receiving _ interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed ? overrun error (note 3) this error occurs when the next data is ready before contents of uarti re- ceive buffer register are read out ? clk polarity selection whether transmit data is output/input at the rising edge or falling edge of the transfer clock can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? continuous receive mode selection reception is enabled simultaneously by a read from the receive buffer register ? transfer clock output from multiple pins selection uart1 transfer clock can be set 2 pins, and can be selected to output from which pin. note 1: n denotes the value 00 16 to ff 16 that is set to the uart bit rate generator. note 2: maximum 5 mbps. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1. item transfer data format transfer clock transmission/reception control transmission start condi- tion reception start condition interrupt request generation timing error detection select function
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 93 figure ga-6. uarti transmit/receive mode register in clock synchronous serial i/o mode (i=0,1) table ga-2 lists the functions of the input/output pins during clock synchronous serial i/o mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n-channel open-drain is selected, this pin is in floating state.) table ga-2. input/output pin functions in clock synchronous serial i/o mode (i=0,1) symbol address when reset uimr(i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode register internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 0 (must always be "0" in clock synchronous serial i/o mode) 01 0 smd0 smd1 smd2 serial i/o mode select bit 0 0 1 : clock synchronous serial i/o mode b2 b1 b0 0 invalid in clock synchronous serial i/o mode pin name function method of selection txdi (p4 4 , p7 4 ) serial data output serial data input transfer clock output transfer clock input programmable i/o port (outputs dummy data when performing reception only) rxdi (p4 5 , p7 5 ) clki (p4 6 , p7 6 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ? port p4 6 , p7 6 direction register (bits 6 at address 03ea 16 and 03ef 16 ) = ? port p4 5 , p7 5 direction register (bits 5 at address 03ea 16 and 03ef 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) =?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 ) = ?? port p4 7 , p7 7 direction register (bits 7 address 03ea 16 and 03ef16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) = ?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) = ? cts input rts output ctsi/rtsi (p4 7 , p7 7 )
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 94 figure ga-7. typical transmit/receive timings in clock synchronous serial i/o mode ? example of transmit timing (when internal clock is selected) ? example of receive timing (when external clock is selected) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 t c t c l k s t o p p e d p u l s i n g b e c a u s e t r a n s f e r e n a b l e b i t = 0 d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r t c = t c l k = 2 ( n + 1 ) / f i f i : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( f 1 , f 8 , f 3 2 ) n : v a l u e s e t t o b r g i t r a n s f e r c l o c k t r a n s m i t e n a b l e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t l ) c l k i t x d i t r a n s m i t r e g i s t e r e m p t y f l a g ( t x e p t ) h l 0 1 0 1 0 1 c t s i s h o w n i n ( ) a r e b i t s y m b o l s . t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : i n t e r n a l c l o c k i s s e l e c t e d . c t s f u n c t i o n i s s e l e c t e d . c l k p o l a r i t y s e l e c t b i t = 0 . t r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t = 0 . t r a n s m i t i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . s t o p p e d p u l s i n g b e c a u s e c t s = h 1 / f e x t d u m m y d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r t r a n s m i t e n a b l e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t l ) c l k i r x d i r e c e i v e c o m p l e t e f l a g ( r l ) r t s i h l 0 1 0 1 0 1 r e c e i v e e n a b l e b i t ( r e ) 0 1 r e c e i v e d a t a i s t a k e n i n t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r r e a d o u t f r o m u a r t i r e c e i v e b u f f e r r e g i s t e r s h o w n i n ( ) a r e b i t s y m b o l s . t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s . e x t e r n a l c l o c k i s s e l e c t e d . r t s f u n c t i o n i s s e l e c t e d . c l k p o l a r i t y s e l e c t b i t = 0 . f e x t : f r e q u e n c y o f e x t e r n a l c l o c k t r a n s f e r r e d f r o m u a r t i r e c e i v e r e g i s t e r t o u a r t i r e c e i v e b u f f e r r e g i s t e r r e c e i v e i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . m e e t t h e f o l l o w i n g c o n d i t i o n s w h e n t h e c l k i n p u t b e f o r e d a t a r e c e p t i o n = h t r a n s m i t e n a b l e b i t 1 r e c e i v e e n a b l e b i t 1 d u m m y d a t a w r i t e t o u a r t i t r a n s m i t b u f f e r r e g i s t e r
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 95 (a) polarity select function as shown in figure ga-8, the clk polarity select bit (bit 6 at addresses 03a4 16 , 03ac 16 ) allows selection of the polarity of the transfer clock. figure ga-8. polarity of transfer clock (b) lsb first/msb first select function as shown in figure ga-9, when the transfer format select bit (bit 7 at addresses 03a4 16 , 03ac 16 ) = 0, the transfer format is lsb first; when the bit = 1, the transfer format is msb first. figure ga-9. transfer format ?when clk polarity select bit = ? note 2: the clki pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 0 t x d i r x d i clk i ?when clk polarity select bit = ? note 1: the clki pin level when not transferring data is ?? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i lsb first ?when transfer format select bit = ? d 1 d 2 d 3 d 4 d 5 d 6 d 7 d0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 t x d i r x d i clk i ?when transfer format select bit = ? d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 d 7 t x d i r x d i clk i msb first note: this applies when the clk polarit y select bit = ??
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock synchronous serial i/o mode 96 (c) transfer clock output from multiple pins function this function allows the setting two transfer clock output pins and choosing one of the two to output a clock by using the clk and clks select bit (bits 4 and 5 at address 03b0 16 ). (see figure ga-10.) the multiple pins function is valid only when the internal clock is selected for uart1. note that when _______ _______ this function is selected, cts/rts function of uart1 cannot be used. figure ga-10. the transfer clock output from the multiple pins function usage (d) continuous receive mode if the continuous receive mode enable bit (bits 2 and 3 at address 03b0 16 ) is set to 1, the unit is placed in continuous receive mode. in this mode, when the receive buffer register is read out, the unit simultaneously goes to a receive enable state without having to set dummy data to the transmit buffer register back again. microcomputer t x d 1 (p7 4 ) clks 1 (p7 7 ) clk 1 (p7 6 ) in clk in clk note: this applies when the internal clock is selected and transmission is p erformed only in clock synchronous serial i/o mode.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 97 (2) clock asynchronous serial i/o (uart) mode the uart allows transmitting and receiving data after setting the desired transfer rate and transfer data format. tables ga-3 lists the specifications of the uart mode. figure ga-11 shows the uarti transmit/ receive mode register. table ga-3. specifications of clock synchronous serial i/o mode item specification transfer data format ?character bit (transfer data): 7 bits, 8 bits or 9 bits as selected ?start bit: 1 bit ?parity bit: odd, even or nothing as selected ?stop bit: 1 bit or 2 bits as selected transfer clock ?when internal clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 = 0) : fi/16(n+1) (note 1) fi = f 1 , f 8 , f 32 ?when external clock is selected (bit 3 at addresses 03a0 16 , 03a8 16 =1) : f ext /16(n+1) (note 1) (note 2) transmission/reception control _______ _______ _______ _______ ?cts function/rts function/cts, rts function chosen to be invalid transmission start condition ?to start transmission, the following requirements must be met: - transmit enable bit (bit 0 at addresses 03a5 16 , 03ad 16 ) = 1 - transmit buffer empty flag (bit 1 at addresses 03a5 16 , 03ad 16 ) = 0 _______ _______ - when cts function is selected, cts input level = l reception start condition ?to start reception, the following requirements must be met: - receive enable bit (bit 2 at addresses 03a5 16 , 03ad 16 ) = 1 - start bit detection interrupt request ?when transmitting generation timing - transmit interrupt cause select bits (bits 0,1 at address 03b0 16 ) = 0: interrupts requested when data transfer from uarti transfer buffer register to uarti transmit register is completed - transmit interrupt cause select bits (bits 0, 1 at address 03b0 16 ) = 1: interrupts requested when data transmission from uarti transfer register is completed ?when receiving - interrupts requested when data transfer from uarti receive register to uarti receive buffer register is completed error detection ?overrun error (note 3) this error occurs when the next data is ready before contents of uarti receive buffer register are read out ?framing error this error occurs when the number of stop bits set is not detected ?parity error this error occurs when if parity is enabled, the number of 1s in parity and character bits does not match the number of 1s set ?error sum flag this flag is set (= 1) when any of the overrun, framing, and parity errors is encountered select function ?sleep mode selection this mode is used to transfer data to and from one of multiple slave microcomputers note 1: n denotes the value 00 16 to ff 16 that is set to the uarti bit rate generator. note 2: f ext is input from the clki pin. note 3: if an overrun error occurs, the uarti receive buffer will have the next data written in. note also that the uarti receive interrupt request bit is not set to 1.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 98 table ga-4 lists the functions of the input/output pins during uart mode. note that for a period from when the uarti operation mode is selected to when transfer starts, the txdi pin outputs a h. (if the n- channel open-drain is selected, this pin is in floating state.) table ga-4. input/output pin functions in uart mode (i=0,1) figure ga-11. uarti transmit/receive mode register in uart mode pin name function method of selection txdi (p4 4 , p7 4 ) serial data output serial data input programmable i/o port transfer clock input programmable i/o port rxdi (p4 5 , p7 5 ) clki (p4 6 , p7 6 ) internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ? internal/external clock select bit (bit 3 at address 03a0 16 , 03a8 16 ) = ?? port p4 5 , p7 5 direction register (bits 5 at address 03ea 16 and 03ef 16 )= ?? (can be used as an input port when performing transmission only) cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) =?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 ) = ?? port p4 7 , p7 7 direction register (bits 7 at address 03ea 16 and 03ef 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) = ?? cts/rts function select bit (bit 2 at address 03a4 16 , 03ac 16 ) = ? cts/rts disable bit (bit 4 at address 03a4 16 , 03ac 16 ) = ? cts input rts output ctsi/rtsi (p4 7 , p7 7 ) (outputs dummy data when performing reception only) symbol address when reset uimr (i=0,1) 03a0 16 , 03a8 16 00 16 ckdir uarti transmit/receive mode register internal/external clock select bit stps pry prye slep 0 : internal clock 1 : external clock bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 smd0 smd1 smd2 serial i/o mode select bit b2 b1 b0 0 : one stop bit 1 : two stop bits 0 : parity disabled 1 : parity enabled 0 : sleep mode deselected 1 : sleep mode selected 1 0 0 : transfer data 7 bits long 1 0 1 : transfer data 8 bits long 1 1 0 : transfer data 9 bits long valid when bit 6 = ? 0 : odd parity 1 : even parity stop bit length select bit odd/even parity select bit parity enable bit sleep select bit
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 99 ? example of transmit timing when transfer data is 8 bits long (parity enabled, one stop bit) ? example of transmit timing when transfer data is 9 bits long (parity disabled, two stop bits) figure ga-12. typical transmit timings in uart mode t r a n s m i t e n a b l e e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t i ) t r a n s m i t r e g i s t e r e m p t y f l a g ( t x e p t ) d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s t p s t a r t b i t p a r i t y b i t t x d i c t s i t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : p a r i t y i s e n a b l e d . o n e s t o p b i t . c t s f u n c t i o n i s s e l e c t e d . t r a n s m i t i n t e r r u p t c a u s e s e l e c t b i t = 1 . 1 0 1 l h 0 1 t c = 1 6 ( n + 1 ) / f i o r 1 6 ( n + 1 ) / f e x t f i : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( f 1 , f 8 , f 3 2 ) f e x t : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( e x t e r n a l c l o c k ) n : v a l u e s e t t o b r g i t r a n s m i t i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s t p s p d 0 d 1 s t t r a n s m i t e n a b l e b i t ( t e ) t r a n s m i t b u f f e r e m p t y f l a g ( t i ) t x d i t r a n s m i t r e g i s t e r e m p t y f l a g ( t x e p t ) 0 1 0 1 0 1 t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : p a r i t y i s d i s a b l e d . t w o s t o p b i t s . c t s f u n c t i o n i s d i s a b l e d . t r a n s m i t i n t e r r u p t c a u s e s s e l e c t b i t = 0 . t r a n s f e r c l o c k t c t c = 1 6 ( n + 1 ) / f i o r 1 6 ( n + 1 ) / f e x t f i : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( f 1 , f 8 , f 3 2 ) f e x t : f r e q u e n c y o f b r g i ' s c o u n t s o u r c e ( e x t e r n a l c l o c k ) n : v a l u e s e t t o b r g i t r a n s m i t i n t e r r u p t r e q u e s t b i t ( i r ) 0 1 s h o w n i n ( ) a r e b i t s y m b o l s . s h o w n i n ( ) a r e b i t s y m b o l s . t c t r a n s f e r c l o c k s p s t o p p e d p u l s i n g b e c a u s e t r a n s m i t e n a b l e b i t = 0 s t o p b i t t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r s t a r t b i t d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s td 8 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s t d 8 d 0 d 1 s t s p s p s t o p b i t s p t h e t r a n s f e r c l o c k s t o p s m o m e n t a r i l y a s c t s i s h w h e n t h e s t o p b i t i s c h e c k e d . t h e t r a n s f e r c l o c k s t a r t s a s t h e t r a n s f e r s t a r t s i m m e d i a t e l y c t s c h a n g e s t o l . d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r s p t r a n s f e r r e d f r o m u a r t i t r a n s m i t b u f f e r r e g i s t e r t o u a r t i t r a n s m i t r e g i s t e r s t o p b i t d a t a i s s e t i n u a r t i t r a n s m i t b u f f e r r e g i s t e r . 0 c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d .
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer clock asynchronous serial i/o (uart) mode 100 ? example of receive timing when transfer data is 8 bits long (parity disabled, one stop bit) figure ga-13. typical receive timing in uart mode (a) sleep mode (uart0, uart1) this mode is used to transfer data between specific microcomputers among multiple microcomputers d 0 d 1 s t a r t b i t s a m p l e d l r e c e i v e d a t a t a k e n i n b r g i ' s c o u n t s o u r c e r e c e i v e e n a b l e b i t r x d i t r a n s f e r c l o c k r e c e i v e c o m p l e t e f l a g r t s i s t o p b i t 1 0 0 1 h l t h e a b o v e t i m i n g a p p l i e s t o t h e f o l l o w i n g s e t t i n g s : p a r i t y i s d i s a b l e d . o n e s t o p b i t . r t s f u n c t i o n i s s e l e c t e d . r e c e i v e i n t e r r u p t r e q u e s t b i t 0 1 c l e a r e d t o 0 b y s o f t w a r e , o r w h e n a n i n t e r r u p t r e q u e s t i s a c c e p t e d . t r a n s f e r r e d f r o m u a r t i r e c e i v e r e g i s t e r t o u a r t i r e c e i v e b u f f e r r e g i s t e r r e c e p t i o n t r i g g e r e d w h e n t r a n s f e r c l o c k i s g e n e l a t e d b y f a l l i n g e d g e o f s t a r t b i t d 7 connected using uarti. the sleep mode is selected when the sleep select bit (bit 7 at addresses 03a0 16 , 03a8 16 ) is set to 1 during reception. in this mode, the unit performs receive operation when the msb of the received data = 1 and does not perform receive operation when the msb = 0.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 101 serial i/o2 serial i/o2 is used as the clock synchronous serial i/o and has an ordinary mode and an automatic transfer mode. in the automatic transfer mode, serial transfer is performed through the serial i/o automatic transfer ram which has up to 256 bytes (addresses 00400 16 to 004ff 16 ). the s rdy2 , s busy2 and s stb2 pins each have a handshake i/o signal function and can select either h active or l active for active logic. specification ? 8-bit serial i/o mode (non-automatic transfer) ? automatic transfer serial i/o mode ? transfer data length: 8 bits ? full duplex mode / transmit-only mode selected by bit 5 at address 0342 16 ? when internal clock is selected (bit 2 at address 0342 16 = 0) : selected by bits 5 to 7 at address 0348 16 ? when external clock is selected (bit 2 at address 034216 = 1) : input from s clk21 pin, s clk22 pin(note 2) ? when internal clock is selected : f(x in )/4, f(x in )/8, f(x in )/16, f(x in )/32, f(x in )/64, f(x in )/128, f(x in )/256 ? when external clock is selected : input cycle 0.95 m s or less ? s stb2 output / s busy2 input or output / s rdy2 input or output chosen ? to start transmission / reception, the following requirements must be met: _ serial i/o initialization bit (bit 4 at address 0342 16 ) = 1 _ when s busy2 input, or s rdy2 input is selected : selected input level = h ____________ _________ _ when s busy2 input, or s rdy2 input is selected : selected input level = l ? furthermore, if external clock is selected, the following requirements must also be met: _ input level of s clk21 or s clk22 = h ? to stop transmission and reception, set serial i/o initialization bit (bit 4 at address 0342 16 ) to 0 regardless internal clock and external clock. ? 8-bit serial i/o mode : interrupts requested when 8-bit data transfer is com- pleted ? automatic transfer serial i/o mode :interrupts requested when last receive data transfer to automatic transfer ram ? s out2 p-channel output disable function cmos output or n-channel open-drain output can be selected ? lsb first/msb first selection whether transmission/reception begins with bit 0 or bit 7 can be selected ? serial i/o2 clock pin select bit serial clock input/output can be selected; s clk21 or s clk22 ? s busy output, s stb2 output select function (only automatic transfer serial mode) s busy output, s stb2 output can be selected; 1-byte data transfer unit or all data transfer unit ? s out2 pin control bit either output active or high-impedance can be selected as a s out2 pin state at serial non-transfer . note 1: it is necessary to set the serial i/o clock pin select bit ( bit 7 at address 0342 16 ) item serial mode transfer data format transfer clock transfer rate transmission/reception control transmission / reception start condition transmission and reception stop condition interrupt request generation timing select function table ga-1. specifications of clock synchronous serial i/o2
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 102 figure ga-1. block diagram of serial i/o2 main data bus serial i/o2 automatic transfer controller local data bus serial i/o automatic transfer ram (00400 16 ?04ff 16 ) serial i/o2 control register 3 x in serial i/o2 automatic transfer data pointer address decoder main address bus local address bus 1/8 1/16 1/32 1/64 1/128 serial i/o2 interrupt request port latch serial i/o2 counter synchronous circuit serial i/o2 synchronous clock selection bit ? port latch s clk21 ? ? s clk2 ? internal synchronous clock selection bits 1/256 port latch s busy2 s stb2 (s stb2 pin control bit) serial transfer status flag ? ? ? ? ? ? port latch s out2 s in2 port latch serial i/o2 register (8) ? ? serial transfer selection bits divider 1/4 serial i/o2 clock pin selection bit s clk22 ? ? port latch ? ? ? ? serial i/o2 clock pin selection bits s rdy2 s rdy2 ? busy2 pin control bit s rdy2 ? busy2 pin control bit
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 103 figure ga-2. serial i/o2 control registers 1, 2 s e r i a l i / o 2 c o n t r o l r e g i s t e r 2 s y m b o la d d r e s sw h e n r e s e t s i o 2 c o n 20 3 4 4 1 6 0 0 1 6 b i t n a m ef u n c t i o n r b i t s y m b o l w b 7b 6b 5b 4 b 3b 2b 1b 0 s r d y 2 s b u s y 2 p i n c o n t r o l b i t s s c o n 2 0 s c o n 2 1 s c o n 2 2 s c o n 2 3 s e r i a l i / o 2 c o n t r o l r e g i s t e r 1 s y m b o la d d r e s sw h e n r e s e t s i o 2 c o n 10 3 4 2 1 6 0 0 1 6 b i t n a m ef u n c t i o n b i t s y m b o l r w b 7b 6b 5b 4b 3b 2b 1b 0 s e r i a l t r a n s f e r s e l e c t b i t s s c o n 1 0 s c o n 1 1 s c o n 1 2 s c o n 1 3 s e r i a l i / o 2 s y n c h r o n o u s c l o c k s e l e c t b i t s ( s s t b 2 p i n c o n t r o l b i t ) 0 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) 0 1 : e x t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n i / o p o r t . ) 1 0 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n s s t b 2 o u t p u t . ) 1 1 : i n t e r n a l s y n c h r o n o u s c l o c k ( s s t b 2 p i n i s a n s s t b 2 o u t p u t . ) 0 : s e r i a l i / o i n i t i a l i z a t i o n 1 : s e r i a l i / o e n a b l e d s e r i a l i / o i n i t i a l i z a t i o n b i t t r a n s f e r m o d e s e l e c t b i t 0 : f u l l d u p l e x ( t r a n s m i t a n d r e c e i v e ) m o d e ( s i n 2 p i n i s a s i n 2 i n p u t . ) 1 : t r a n s m i t - o n l y m o d e ( s i n 2 p i n i s a n i / o p o r t . ) s c o n 1 4 s c o n 1 5 s e r i a l i / o 2 c l o c k p i n s e l e c t b i t t r a n s f e r d i r e c t i o n s e l e c t b i t s c o n 1 6 s c o n 1 7 0 0 : s e r i a l i / o d i s a b l e d ( s e r i a l i / o p i n s a r e i / o p o r t s ) 0 1 : 8 - b i t s s e r i a l i / o 1 0 : i n h i b i t 1 1 : a u t o m a t i c t r a n s f e r s e r i a l i / o ( 8 - b i t s ) 0 : l s b f i r s t 1 : m s b f i r s t 0 : s c l k 2 1 ( s c l k 2 2 p i n i s a n i / o p o r t . ) 1 : s c l k 2 2 ( s c l k 2 1 p i n i s a n i / o p o r t . ) 0 : f u n c t i o n s a s e a c h 1 - b y t e s i g n a l 1 : f u n c t i o n s a s s i g n a l f o r a l l t r a n s f e r d a t a s b u s y 2 o u t p u t s s t b 2 o u t p u t f u n c t i o n s e l e c t b i t ( v a l i d i n a u t o m a t i c t r a n s f e r m o d e ) s e r i a l t r a n s f e r s t a t u s f l a g 0 : s e r i a l t r a n s f e r c o m p l e t i o n 1 : s e r i a l t r a n s f e r r i n g s c o n 2 4 s c o n 2 5 s o u t 2 p - c h a n n e l o u t p u t d i s a b l e b i t s o u t 2 p i n c o n t r o l b i t ( a t n o - t r a n s f e r s e r i a l d a t a ) s c o n 2 6 s c o n 2 7 0 : o u t p u t a c t i v e 1 : o u t p u t h i g h - i m p e d a n c e 0 : c m o s 3 - s t a t e ( p - c h a n n e l o u t p u t i s v a l i d . ) 1 : n - c h a n n e l o p e n - d r a i n ( p - c h a n n e l o u t p u t i s i n v a l i d . ) b 3 b 2 b 1 b 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 1 1 0 1 1 1 1 0 1 1 1 1 s r d y 2 p i ns b u s y 2 p i n i / o p o r ti / o p o r t n o t u s e d s r d y 2 o u t p u ti / o p o r t s r d y 2 o u t p u ti / o p o r t i / o p o r ts b u s y 2 i n p u t i / o p o r ts b u s y 2 i n p u t i / o p o r ts b u s y 2 o u t p u t i / o p o r ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 i n p u ts b u s y 2 o u t p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t s r d y 2 o u t p u ts b u s y 2 i n p u t b 1 b 0 b 3 b 2
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 104 figure ga-3. serial i/o2 automatic transfer data pointer serial i/o2 control register 3 symbol address when reset sio2con3 0348 16 00000000 2 bit name function bit symbol rw b7 b6 b5 b4 b3 b2 b1 b0 automatic transfer interval set bits ttran0 ttran1 ttran2 ttran3 internal synchronous clock selection bits 000:f(x in )/4 001:f(x in )/8 010:f(x in )/16 011:f(x in )/32 100:f(x in )/64 101:f(x in )/128 110:f(x in )/256 ttran4 tclk0 tclk1 tclk2 00000 :2 cycles of transfer clocks 00001 :3 cycles of transfer clocks : 11110 :32 cycles of transfer clocks 11111 :33 cycles of transfer clocks data is written to a latch and read from a decrement counter. b4b3b2b1b0 b7b6b5 serial i/o2 automatic transfer data pointer symbol address when reset sio2dp 0340 16 00 16 function r w b7 b6 b5 b4 b3 b2 b1 b0 ?automatic transfer data pointer set specify the low-order 8 bits of the first data store address on the serial i/o automatic transfer ram. data is written into the latch and read from the decrement counter. serial i/o2 register/transfer counter symbol address when reset sio2 0346 16 00 16 function r w b7 b6 b5 b4 b3 b2 b1 b0 ?number of automatic transfer data set set the number of automatic transfer data. set a value one less than number of transfer data. data is written into the latch and read from the decrement counter.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 105 table ga-2. functions of the serial i/o2 input/output pins table ga-2 lists the functions of the serial i/o2 input/output pins pin name function method of selection s out2 (p9 4 ) serial data output serial data input transfer clock output transfer clock input port p9 4 direction register (bit 4 at address 03f3 16 )= ?? s out2 p-channel output disable bit (bit 7 at address 0344 16 )= ??, ?? s out2 pin control bit (bit 6 at address 0344 16 )= ??, ?? (outputs dummy data when performing reception only) s in2 (p9 3 ) s clk21 (p9 5 ) serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?0?, ?1 serial i/o2 clock pin select bit (bit 7 at address 0342 16 ) = ? serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?1?, ?1 serial i/o2 clock pin select bit (bit 7 at address 0342 16 ) = ? port p9 5 direction register (bit 5 at address 03f3 16 )= ? port p9 3 direction register (bit 4 at address 03f3 16 )= ?? transfer mode select bit (bit 5 at address 0342 16 )= ? (input/output port when transfer mode select bit (bit 5 at address 0342 16 )= ?? transfer clock output transfer clock input s clk22 (p9 6 ) serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?0?, ?1 serial i/o2 clock pin select bit (bit 7 at address 0342 16 ) = ? serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?1?, ?1 serial i/o2 clock pin select bit (bit 7 at address 0342 16 ) = ? port p9 6 direction register (bit 6 at address 03f3 16 )= ? s rdy input / output s rdy2 (p9 0 ) set by s rdy2 ?s busy2 pin control bits (bits 0 to 3 at address 0344 16 ) s busy input / output s busy2 (p9 1 ) set by s rdy2 ?s busy2 pin control bits (bits 0 to 3 at address 0344 16 ) s busy2 output ?s stb2 output function select bit (bit 4 at address 0344 16 )= ??, ? s stb input / output s stb2 (p9 2 ) serial i/o2 synchronous clock select bits (bits 2, 3 at address 0342 16 ) = ?0?, ?1 s busy2 output ?s stb2 output function select bit (bit 4 at address 0344 16 )= ??, ? s out2 output either output active or high-impedance can be selected as a s out2 pin state at serial non-transfer by the s out2 pin control bit (bit 6 of address 0344 16 ). however, when the external synchronous clock is selected, perform the following setup to put the s out2 pin into a high-impedance state. when the s clk2i ( i = 1, 2) input is h after completion of transfer, set the s out2 pin control bit to 1. when the s clk2i ( i = 1, 2) input goes to l after the start of the next serial transfer, the s out2 pin control bit is automatically reset to 0 and put into an output active state.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 106 serial i/o2 mode there are two types of serial i/o2 modes: 8-bit serial i/o mode where automatic transfer ram is not used, and an automatic transfer serial i/o mode. (1) 8-bit serial i/o mode address 0346 16 is assigned to the serial i/o2 register. when the internal synchronous clock is selected, a serial transfer of the 8-bit serial i/o is started by a write signal to the serial i/o2 register (address 0346 16 ). the serial transfer status flag (bit 5 of address 0344 16 ) is set to 1 by writing into the serial i/o2 register and reset to 0 after completion of 8-bit transfer. at the same time, a serial i/o2 interrupt request occurs. if the transfer is completed, the receive data is read out from serial i/o2 register. when the external synchronous clock is selected, the contents of the serial i/o2 register are con- tinuously shifted while transfer clocks are input to s clk21 or s clk22 . therefore, the clock needs to be controlled externally. (2) automatic transfer serial i/o mode address 0346 16 is assigned to the transfer counter (1-byte units). the serial i/o2 automatic trans- fer controller controls the write and read operations of the serial i/o2 register. the serial i/o auto- matic transfer ram is mapped to addresses 00400 16 to 004ff 16 . before starting transfer, make sure the 8 low-order bits of the address that contains the beginning data to be serially transferred is set to the automatic transfer data pointer (address 0340 16 ). when the internal synchronous clock is selected, the transfer interval is inserted between one data and another in the following cases: 1. when using no handshake signal 2. when using the s rdy2 output, s busy2 output, and s stb2 output of the handshake signal inde pendently 3. when using a combination of s rdy2 output and s stb2 output or a combination of s busy2 output and s stb2 output of the handshake signal the transfer interval can be set in the range of 2 to 23 cycles using the automatic transfer interval set bit (bits 0C4 of address 0348 16 ). also, when using s busy2 output as a signal for each occurrence of the all transfer data, a transfer interval is inserted before the system starts sending or receiving the first data and after the system finished sending or receiving the last data, not just between one data and another. furthermore, when using s stb2 output, the transfer interval between each 1-byte data is extended by 2 cycles from the set value no matter how the s busy2 output. s stb2 output function select bit (bit 4 of address 0344 16 ) is set. when using s busy2 output and s stb2 output in combination as a signal for each occurrence of the all transfer data, the transfer interval after the system finished sending or receiving the last data is extended by 2 cycles from the set value. when an external synchronous clock is selected, the automatic transfer interval is disabled.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 107 figure ga-5. automatic transfer serial i/o operation 004ff 16 automatic transfer ram transfer counter automatic transfer data pointer serial i/o2 re g ister 00452 16 00451 16 00450 16 0044f 16 0044e 16 00400 16 04 16 52 16 s in2 s out2 when the internal synchronous clock is selected, automatic serial transfer starts by writing 1 less than the number of transfer bytes to the transfer counter (address 0346 16 ). when an external sync clock is selected, automatic serial transfer starts by writing 1 less than the number of transfer bytes to the transfer counter and the transfer clock is input. in this case, allow for at least 5 cycles of internal system clock before the transfer clock is input after writing to the transfer counter. also, for data to data transfer intervals, allow at least 5 cycles of internal system clock reckoning from a rise of clock at the last bit of one-byte data. regardless of whether the internal or external synchronous clock is selected, the automatic transfer data pointer and the transfer counter are decreased after each 1-byte data is received and then written into the automatic transfer ram. the serial transfer status flag (bit5 of address 0344 16 ) is set to 1 by writing data into the transfer counter. the serial transfer status flag is reset to 0 after the last data is written into the automatic transfer ram. at the same time, a serial i/o2 interrupt request occurs. the values written in the automatic transfer data pointer (address 0340 16 ) and the automatic transfer interval set bits (bit 0 to bit 4 of address 0348 16 ) are held in the latch. when data is written into the transfer counter, the values latched in the automatic transfer data pointer (address 0340 16 ) and the automatic transfer interval set bits (bit 0 to bit 4) are transferred to the decrement counter.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 108 handshake signal there are five types of handshake signal : s stb2 output, s busy2 input/ output , and s rdy2 input/output. (1) s stb2 output signal the s stb2 output is a signal to inform an end of transmission/reception to the serial transfer destina- tion. the s stb2 output signal can be used only when the internal synchronous clock is selected. in the initial status [ serial i/o initialization bit (bit 4 of address 0342 16 ) = 0 ], the s stb2 output goes to l __________ (bits 2, 3 of address 0342 16 =11), or the s stb2 output goes to h (bits 2, 3 of address 0342 16 =10). at the end of transmit/receive operation, after the all data of the serial i/o2 register ( address 0346 16 ) is _________ output from s out2 , s stb2 output is h (or s stb2 output is l) in the period of 1 cycle of the transfer clock. furthermore, after 1 cycle, the serial transfer status flag (bit 5 of address 0344 16 ) is reset to 0. in the automatic transfer serial i/o mode, whether the s stb2 output is to be output at an end of each 1-byte data or after completion of transfer of all data can be selected by the s busy2 output ? s stb2 output function select bit (bit 4 of address 0344 16 ). figure ga-6. s stb2 output operation "1" "0" s stb2 (output) "h" "l" d 0 tc d 1 d 2 d 3 d 4 d 5 d 6 d 7 "1" "0" "h" "l" d 0 tc d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 automatic transfer interval ?erial operation used s stb2 output operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock s stb2 output timing : each 1-byte data internal clock serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i=1, 2)(output) s out2 tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 ?erial operation used s stb2 output operation mode : automatic transfer serial i/o mode transfer clock : internal synchronous clock s stb2 output timing : each transfer of all data internal clock serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i=1, 2)(output) s stb2 (output) s out2 tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 109 figure ga-8. s busy2 input operation (2) figure ga-7. s busy2 input operation (1) (2) s busy2 input signal the s busy2 input is a signal requested to stop of transmission/reception from the serial transfer des- tination. when the internal synchronous clock is selected, input a h level signal into the s busy2 input (or a l ___________ level signal into the s busy2 input) in the initial status [serial i/o initialization bit (bit 4 of address ____________ 0342 16 ) = 0]. when a l level signal into the s busy2 ( or h on s busy2 ) input for 1.5 cycles or more of transfer clock, transfer clocks are output from s clk2i (i = 1, 2) , and transmit/receive operation is ____________ started. when s busy2 input is driven h (or s busy2 input is driven l) during transmit/receive operation, the transfer clock being output from s clk2i (i = 1, 2) remains active until after the system finishes sending or receiving the designated number of bits, without stopping the transmit/receive operation immediately. the handshake unit of the 8-bit serial i/o is 8 bits, and that of the automatic transfer serial i/o is 8 bits. internal clock "1" "0" "h" "l" tc d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1.5 cycle or more ?erial operation used s busy2 input operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock s busy2 input timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(output) s out2 s busy2 (input ) tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 "1" "0" "h" "l" note: the last output data d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 invalid note ?erial operation used s busy2 input operation mode : 8-bit serial i/o mode transfer clock : external synchronous clock s busy2 input timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(input ) s out2 s busy2 (input ) high-impedance high-impedance when the external synchronous clock is selected, input a h level signal into the s busy2 input (or a l ___________ level signal into the s busy2 input) in the initial status[serial i/o initialization bit (bit 4 of address 0342 16 ) = 0]. at this time, the transfer clock become invalid. the transfer clock become valid while a l level ___________ signal is input into the s busy2 input (or a h level signal into the s busy2 input) and transmit/receive operation work. ___________ when changing the input values into the s busy2 (or s busy2 ) input at these operations, change them when the transfer clock input is in a h state. when the high-impedance of the s out2 output is selected by the s out2 pin control bit (bit 6 of address 0344 16 ), the s out2 becomes high-impedance, ___________ while a h level signal is input into the s busy2 input (or a l level signal into the s busy2 input.)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 110 figure ga-9. s busy2 output operation (1) figure ga-10. s busy2 output operation (2) internal clock "1" "0" "h" "l" d 0 tc tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 d 1 d 2 d 3 d 4 d 5 d 6 d 7 ?erial operation used s busy2 output operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock s busy2 output timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s out2 s clk2i (i = 1, 2)(output) s busy2 (output ) "1" "0" "h" "l" d 0 s out2 d 1 d 2 d 3 d 4 d 5 d 6 d 7 write to serial i/o register (address 0346 16 ) ?erial operation used s busy2 output operation mode : 8-bit serial i/o mode transfer clock : external synchronous clock s busy2 output timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(input) s busy2 (output) (3) s busy2 output signal the s busy2 output is a signal which requests to stop of transmission/reception to the serial transfer destination. in the automatic transfer serial i/o mode, regardless of the internal or external synchro- nous clock, whether the s busy2 output is to be output at transfer of each 1-byte data or during transfer of all data can be selected by the s busy2 output ? s stb2 output function select bit (bit 4 of address 0344 16 ). in the initial status[ serial i/o initialization bit (bit 4 of address 0342 16 ) = 0 ], the status in ____________ which the s busy2 outputs h (or the s busy2 outputs l). when the internal synchronous clock is selected, in the 8-bit serial i/o mode and the automatic trans- fer serial i/o mode (s busy2 output function: each 1-byte signal is selected), the s busy2 output goes to ____________ l (or the s busy2 output goes to h) before 0.5 cycle of the timing at which the transfer clock goes to l . in the automatic transfer serial i/o mode (the s busy2 output function: all transfer data is selected), ____________ the s busy2 output goes to l (or the s busy2 output goes to h) when the first transmit data is written into the serial i/o2 register (address 0346 16 ). ____________ when the external synchronous clock is selected, the s busy2 output goes to l (or the s busy2 output goes to h) when transmit data is written into the serial i/o2 register(address 0346 16 ), regardless of the serial i/o transfer mode. at termination of transmit/receive operation, in the 8-bit serial i/o mode, the s busy2 output goes to h ____________ (or the s busy2 output returns to l), when the serial transfer status flag is set to 0, regardless of whether the internal or external synchronous clock is selected. furthermore, in the automatic transfer serial i/o mode (s busy2 output function: each 1-byte signal is selected), the s busy2 output goes to h ____________ (or the s busy2 output goes to l) each time 1-byte of receive data is written into the automatic trans- fer ram.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 111 figure ga-11. s busy2 output operation (3) internal clock "1" "0" "h" "l" d 0 tc d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 automatic transfer interval automatic transfer ram serial i/o2 register serial i/o2 register automatic transfer ram ?erial operation used s busy2 output operation mode : automatic transfer serial i/o mode transfer clock : internal synchronous clock s busy2 output timing : each 1-byte data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(output) s out2 tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 s busy2 (output) internal clock "1" "0" "h" "l" d 0 tc d 1 d 2 d 3 d 4 d 5 d 6 d 7 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 automatic transfer interval automatic transfer ram serial i/o2 register serial i/o2 register automatic transfer ram ?erial operation used s busy2 output operation mode : automatic transfer serial i/o mode transfer clock : internal synchronous clock s busy2 output timing : each transfer of all data serial transfer status flag (bit 5 at address 0344 16 ) s clk2i (i = 1, 2)(output) s out2 tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 s busy2 (output)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 112 figure ga-12. s rdy2 output operation figure ga-13. s rdy2 input operation ?erial operation used s rdy2 output internal clock s rdy2 (output) "h" "l" tc tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 s clk2i (i = 1, 2) (output) s out2 operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock "1" "0" serial transfer status flag (bit 5 at address 0344 16 ) ?erial operation used s rdy2 input internal clock "1" "0" s rdy2 (input ) "h" "l" tc tc : internal synchronous clock is selected by bits 5 to 7 of address 0348 16 d 0 d 1 d 2 d 3 d 4 d 5 d 6 d 7 1.5 cycle or more s clk2i (i = 1, 2) (output) s out2 operation mode : 8-bit serial i/o mode transfer clock : internal synchronous clock serial transfer status flag (bit 5 at address 0344 16 ) (4) s rdy2 output signal the s rdy2 output is a transmit/receive enable signal which informs the serial transfer destination that transmit/receive is ready. in the initial status[serial i/o initialization bit (bit 4 of address 0342 16 ) = 0 ], __________ the s rdy2 output goes to l (or the s rdy2 output goes to h). when the transmitted data is written to __________ the serial i/o2 register (address 0346 16 ), the s rdy2 output goes to h (or the s rdy2 output goes to l). when a transmit/receive operation is started and the transfer clock goes to l, the s rdy2 output __________ goes to l (or the s rdy2 output goes to h). (5) s rdy2 input signal the s rdy2 input is a signal for receiving a transmit/receive ready completion signal from the serial transfer destination. the s rdy2 input signal becomes valid only when the s rdy2 input and the s busy2 output are used. when the internal synchronous clock is selected, input a l level signal into the s rdy2 input (or a h __________ level signal into the s rdy2 input) in the initial status[serial i/o initialization bit (bit 4 of address 0342 16 ) __________ = 0 ]. when a h level signal is input into the s rdy2 input (or a l level signal is input into the s rdy2 input) for a period of 1.5 cycles or more of transfer clock, transfer clocks are output from the s clk2i (i = __________ 1, 2) output and a transmit/receive operation is started. when s rdy2 input is driven l (or s rdy2 input is driven h) during transmit/receive operation, the transfer clock being output from s clk2i (i = 1, 2) remains active until after the system finishes sending or receiving the designated number of bits, without stopping the transmit/receive operation immediately. the handshake unit of the 8-bit serial i/o is 8 bits, and that of the automatic transfer serial i/o is 8 bits. when the external synchronous clock is selected, the s rdy2 input becomes one of the triggers to ____________ output the s busy2 signal. to start a transmit/receive operation (s busy2 output: l, (or s busy2 output: __________ h)), input a h level signal into the s rdy2 input (or a l level signal into the s rdy2 input,) and also write transmit data into the serial i/o2 register (address 0346 16 ).
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer serial i/o2 113 figure ga-14. handshake operation at serial i/o2 mutual connecting (1) figure ga-15. handshake operation at serial i/o2 mutual connecting (2) a: b: s clk2i (i = 1, 2) s rdy2 s busy2 s busy2 s rdy2 s clk2i (i = 1, 2) a: b: write to serial i/o2 re g ister s clk2i (i = 1, 2) s rdy2 s busy2 internal synchronous clock selection external synchronous clock selection write to serial i/o2 register a: b: s clk2i (i= 1, 2) s rdy2 s busy2 s busy2 s rdy2 s clk2i (i= 1, 2) a: b: write to serial i/o2 re g ister s clk2i (i= 1, 2) s rdy2 s busy2 internal synchronous clock selection external synchronous clock selection write to serial i/o2 register
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 114 item performance method of a-d conversion successive approximation (capacitive coupling amplifier) analog input voltage (note 1) 0v to av cc (v cc ) operating clock f ad (note 2) v cc = 5v f ad /divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) v cc = 3v divide-by-2 of f ad /divide-by-4 of f ad , f ad =f(x in ) resolution 8-bit or 10-bit (selectable) absolute precision v cc = 5v ? without sample and hold function 3lsb ? with sample and hold function (8-bit resolution) 2lsb ? without sample and hold function (10-bit resolution) 3lsb v cc = 3v ? without sample and hold function (8-bit resolution)(note 3) 2lsb operating modes one-shot mode, repeat mode, single sweep mode, repeat sweep mode 0, and repeat sweep mode 1 analog input pins 8pins (an 0 to an 7 ) a-d conversion start condition ?software trigger a-d conversion starts when the a-d conversion start flag changes to 1 conversion speed per pin ?without sample and hold function 8-bit resolution: 49 f ad cycles, 10-bit resolution: 59 f ad cycles ? with sample and hold function 8-bit resolution: 28 f ad cycles, 10-bit resolution: 33 f ad cycles note 1: does not depend on use of sample and hold function. note 2: without sample and hold function, set the f ad frequency to 250khz min. with the sample and hold function, set the f ad frequency to 1mhz min. note 3: only mask rom version. a-d converter the a-d converter consists of one 10-bit successive approximation a-d converter circuit with a capacitive coupling amplifier. pins p10 0 to p10 7 also function as the analog signal input pins. the direction registers of these pins for a-d conversion must therefore be set to input. the vref connect bit (bit 5 at address 03d7 16 ) can be used to isolate the resistance ladder of the a-d converter from the reference voltage input pin (v ref ) when the a-d converter is not used. doing so stops any current flowing into the resistance ladder from v ref , reducing the power dissipation. when using the a-d converter, start a-d conversion only after setting bit 5 of 03d7 16 to connect v ref . the result of a-d conversion is stored in the a-d registers of the selected pins. when set to 10-bit precision, the low 8 bits are stored in the even addresses and the high 2 bits in the odd addresses. when set to 8-bit precision, the low 8 bits are stored in the even addresses. table ja-1 shows the performance of the a-d converter. figure ja-1 shows the block diagram of the a-d converter, and figures ja-2 and ja-3 show the a-d converter-related registers. table ja-1. performance of a-d converter
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 115 figure ja-1. block diagram of a-d converter 1 / 2 a d 1 / 2 f a d a - d c o n v e r s i o n r a t e s e l e c t i o n ( 0 3 c 1 1 6 , 0 3 c 0 1 6 ) ( 0 3 c 3 1 6 , 0 3 c 2 1 6 ) ( 0 3 c 5 1 6 , 0 3 c 4 1 6 ) ( 0 3 c 7 1 6 , 0 3 c 6 1 6 ) ( 0 3 c 9 1 6 , 0 3 c 8 1 6 ) ( 0 3 c b 1 6 , 0 3 c a 1 6 ) ( 0 3 c d 1 6 , 0 3 c c 1 6 ) ( 0 3 c f 1 6 , 0 3 c e 1 6 ) c k s 1 = 1 c k s 0 = 0 a - d r e g i s t e r 0 ( 1 6 ) a - d r e g i s t e r 1 ( 1 6 ) a - d r e g i s t e r 2 ( 1 6 ) a - d r e g i s t e r 3 ( 1 6 ) a - d r e g i s t e r 4 ( 1 6 ) a - d r e g i s t e r 5 ( 1 6 ) a - d r e g i s t e r 6 ( 1 6 ) a - d r e g i s t e r 7 ( 1 6 ) r e s i s t o r l a d d e r s u c c e s s i v e c o n v e r s i o n r e g i s t e r a n 0 a n 1 a n 2 a n 3 a n 5 a n 6 a n 7 a - d c o n t r o l r e g i s t e r 0 ( a d d r e s s 0 3 d 6 1 6 ) a - d c o n t r o l r e g i s t e r 1 ( a d d r e s s 0 3 d 7 1 6 ) v r e f v i n v c u t = 0 d a t a b u s h i g h - o r d e r d a t a b u s l o w - o r d e r v r e f a v s s a n 4 v c u t = 1 c k s 0 = 1 c k s 1 = 0 c h 2 , c h 1 , c h 0 = 0 0 0 c h 2 , c h 1 , c h 0 = 0 0 1 c h 2 , c h 1 , c h 0 = 0 1 0 c h 2 , c h 1 , c h 0 = 0 1 1 c h 2 , c h 1 , c h 0 = 1 0 0 c h 2 , c h 1 , c h 0 = 1 0 1 c h 2 , c h 1 , c h 0 = 1 1 0 c h 2 , c h 1 , c h 0 = 1 1 1 d e c o d e r c o m p a r a t o r a d d r e s s e s
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 116 figure ja-2. a-d converter-related registers (1) a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected ch0 ch1 ch2 a-d operation mode select bit 0 0 0 : one-shot mode 0 1 : repeat mode 1 0 : single sweep mode 1 1 : repeat sweep mode 0 repeat sweep mode 1 md0 md1 must always be ?? adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : repeat sweep mode 1 0 : vref not connected 1 : vref connected must always be ?? w r b2 b1 b0 b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pin) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. 0 0 0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 117 figure ja-3. a-d converter-related registers (2) eight low-order bits of a-d conversion result a-d control register 2 (note) symbol address when reset adcon2 03d4 16 xxxxxxx0 2 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 a-d conversion method select bit 0 without sample and hold 1 with sample and hold smp nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? a-d register i symbol address when reset adi (i=0 to 7) 03c0 16 to 03cf 16 indeterminate function w r (b15) b7 b7 b0 b0 (b8) ?during 10-bit mode two high-order bits of a-d conversion result nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? ?during 8-bit mode when read, the content is indeterminate note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 118 (1) one-shot mode in one-shot mode, the pin selected using the analog input pin select bit is used for one-shot a-d conversion. table ja-2 shows the specifications of one-shot mode. figure ja-4 shows the a-d control register in one-shot mode. table ja-2. one-shot mode specifications item specification function the pin selected by the analog input pin select bit is used for one a-d conversion start condition writing 1 to a-d conversion start flag stop condition ?end of a-d conversion (a-d conversion start flag changes to 0) ?writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin figure ja-4. a-d conversion register in one-shot mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 r bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0: f ad /4 is selected 1: f ad /2 is selected cks0 w 0 0 a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 0 : any mode other than repeat sweep mode 1 1 : vref connected w r invalid in one-shot mode 0 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected b2 b1 b0 0 0 : one-shot mode b4 b3 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. must always be ?? must always be ?? 0 0 0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 119 (2) repeat mode in repeat mode, the pin selected using the analog input pin select bit is used for repeated a-d conversion. table ja-3 shows the specifications of repeat mode. figure ja-5 shows the a-d control register in repeat mode. table ja-3. repeat mode specifications item specification function the pin selected by the analog input pin select bit is used for repeated a-d conversion star condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin one of an 0 to an 7 , as selected reading of result of a-d converter read a-d register corresponding to selected pin figure ja-5. a-d conversion register in repeat mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r 01 0 0 0 : an 0 is selected 0 0 1 : an 1 is selected 0 1 0 : an 2 is selected 0 1 1 : an 3 is selected 1 0 0 : an 4 is selected 1 0 1 : an 5 is selected 1 1 0 : an 6 is selected 1 1 1 : an 7 is selected b2 b1 b0 0 1 : repeat mode b4 b3 note: if the a-d control register is rewritten during a-d conversion, the conversin result is indeterminate. a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit a-d operation mode select bit 1 1 : vref connected w r invalid in repeat mode 0 1 frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 0 : any mode other than repeat sweep mode 1 note: if the a-d control register is rewritten during a-d conversion, the conversn result is indeterminate. 0 0 0 must always be ?? must always be ??
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 120 (3) single sweep mode in single sweep mode, the pins selected using the a-d sweep pin select bit are used for one-by-one a-d conversion. table ja-4 shows the specifications of single sweep mode. figure ja-6 shows the a-d control register in single sweep mode. table ja-4. single sweep mode specifications item specification function the pins selected by the a-d sweep pin select bit are used for one-by-one a-d conversion start condition writing 1 to a-d converter start flag stop condition ?end of a-d conversion (a-d conversion start flag changes to 0, except when external trigger is selected) ?writing 0 to a-d conversion start flag interrupt request generation timing end of a-d conversion input pin an 0 and an 1 (2 pins), an 0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin figure ja-6. a-d conversion register in single sweep mode a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 1 0 : single sweep mode md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 0 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 10 invalid in single sweep mode 0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when single sweep and repeat sweep mode 0 are selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 must always be ?? must always be ?? 0 0 0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 121 (4) repeat sweep mode 0 in repeat sweep mode 0, the pins selected using the a-d sweep pin select bit are used for repeat sweep a-d conversion. table ja-5 shows the specifications of repeat sweep mode 0. figure ja-7 shows the a- d control register in repeat sweep mode 0. table ja-5. repeat sweep mode 0 specifications item specification function the pins selected by the a-d sweep pin select bit are used for repeat sweep a-d conversion start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin an 0 and an 1 (2 pins), an0 to an 3 (4 pins), an 0 to an 5 (6 pins), or an 0 to an 7 (8 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) figure ja-7. a-d conversion register in repeat sweep mode 0 a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 0 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 1 : any mode other than repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 1 invalid in repeat sweep mode 0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 , an 1 (2 pins) 0 1 : an 0 to an 3 (4 pins) 1 0 : an 0 to an 5 (6 pins) 1 1 : an 0 to an 7 (8 pins) b1 b0 0 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 must always be ?? must always be ?? 0 0 0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 122 item specification function all pins perform repeat sweep a-d conversion, with emphasis on the pin or pins selected by the a-d sweep pin select bit example : an 0 selected -> an 0 -> an 1 -> an 0 -> an 2 -> an 0 -> an 3 , etc start condition writing 1 to a-d conversion start flag stop condition writing 0 to a-d conversion start flag interrupt request generation timing none generated input pin emphasis on the pin an 0 (1 pin), an 0 and an 1 (2 pins), an 0 to an 2 (3 pins), an 0 to an 3 (4 pins) reading of result of a-d converter read a-d register corresponding to selected pin (at any time) (5) repeat sweep mode 1 in repeat sweep mode 1, all pins are used for a-d conversion with emphasis on the pin or pins selected using the a-d sweep pin select bit. table ja-6 shows the specifications of repeat sweep mode 1. figure ja-8 shows the a-d control register in repeat sweep mode 1. table ja-6. repeat sweep mode 1 specifications figure ja-8. a-d conversion register in repeat sweep mode 1 a-d control register 0 (note) symbol address when reset adcon0 03d6 16 00000xxx 2 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 analog input pin select bit ch0 ch1 ch2 a-d operation mode select bit 0 1 1 : repeat sweep mode 1 md0 md1 adst a-d conversion start flag 0 : a-d conversion disabled 1 : a-d conversion started frequency select bit 0 0 : f ad /4 is selected 1 : f ad /2 is selected cks0 w r a-d control register 1 (note) symbol address when reset adcon1 03d7 16 00 16 bit name function bit symbol b7 b6 b5 b4 b3 b2 b1 b0 a-d sweep pin select bit scan0 scan1 md2 bits 8/10-bit mode select bit 0 : 8-bit mode 1 : 10-bit mode vcut vref connect bit 1 : repeat sweep mode 1 a-d operation mode select bit 1 1 : vref connected w r 1 1 invalid in repeat sweep mode 0 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. b4 b3 when repeat sweep mode 1 is selected 0 0 : an 0 (1 pins) 0 1 : an 0 , an 1 (2 pins) 1 0 : an 0 to an 2 (3 pins) 1 1 : an 0 to an 3 (4 pins) b1 b0 1 1 note: if the a-d control register is rewritten during a-d conversion, the conversion result is indeterminate. frequency select bit 1 0 : f ad /2 or f ad /4 is selected 1 : f ad is selected cks1 must always be ?? must always be ?? 0 0 0
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer a-d converter 123 (a) sample and hold sample and hold is selected by setting bit 0 of the a-d control register 2 (address 03d4 16 ) to 1. when sample and hold is selected, the rate of conversion of each pin increases. as a result, 28 f ad cycles are achieved with 8-bit resolution and 33 f ad cycles with 10-bit resolution. sample and hold can be selected in all modes. however, in all modes, be sure to specify before starting a-d conversion whether sample and hold is to be used.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer d-a converter 124 d-a converter this is an 8-bit, r-2r type d-a converter. the microcomputer contains two independent d-a converters of this type. d-a conversion is performed when a value is written to the corresponding d-a register. bits 0 and 1 (d-a output enable bits) of the d-a control register decide if the result of conversion is to be output. do not set the target port to output mode if d-a conversion is to be performed. output analog voltage (v) is determined by a set value (n : decimal) in the d-a register. v = v ref x n/ 256 (n = 0 to 255) v ref : reference voltage table jb-1 lists the performance of the d-a converter. figure jb-1 shows the block diagram of the d-a converter. figure jb-2 shows the d-a control register. figure jb-3 shows the d-a converter equivalent circuit. table jb-1. performance of d-a converter item performance conversion method r-2r method resolution 8 bits analog output pin 2 channels figure jb-1. block diagram of d-a converter aaaaaaa aaaaaaa p9 7 /da 0 /clk out /dim out aaaaaa p9 6 /da 1 /sclk 22 data bus low-order bits d-a register0 (8) r-2r resistor ladder d-a0 output enable bit d-a register1 (8) r-2r resistor ladder d-a1 output enable bit (address 03d8 16 ) (address 03da 16 )
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer d-a converter 125 figure jb-2. d-a control register d-a control register symbol address when reset dacon 03dc 16 00 16 b7 b6 b5 b4 b3 b2 b1 b0 d-a0 output enable bit da0e bit symbol bit name function r w 0 : output disabled 1 : output enabled d-a1 output enable bit 0 : output disabled 1 : output enabled da1e nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be ?? d-a register symbol address when reset dai (i = 0,1) 03d8 16 , 03da 16 indeterminate w r b7 b0 function r w output value of d-a conversion figure jb-3. d-a converter equivalent circuit v ref av ss 2r r 2r r 2r r 2r r 2r r 2r r 2r r 2r 2r da0 msb lsb d-a0 output enable bit "0" "1" d-a0 register0 note 1: the above diagram shows an instance in which the d-a register is assigned 2a 16 . note 2: the same circuit as this is also used for d-a1. note 3: to reduce the current consumption when the d-a converter is not used, set the d-a output enable bit to 0 and set the d- a register to 00 16 so that no current flows in the resistors rs and 2rs.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer crc calculation circuit 126 crc calculation circuit the cyclic redundancy check (crc) calculation circuit detects an error in data blocks. the microcom- puter uses a generator polynomial of crc_ccitt (x 16 + x 12 + x 5 + 1) to generate crc code. the crc code is a 16-bit code generated for a block of a given data length in multiples of 8 bits. the crc code is set in a crc data register each time one byte of data is transferred to a crc input register after writing an initial value into the crc data register. generation of crc code for one byte of data is com- pleted in two machine cycles. figure uc-1 shows the block diagram of the crc circuit. figure uc-2 shows the crc-related registers. figure uc-3 shows the calculation example using the crc calculation circuit figure uc-2. crc-related registers figure uc-1. block diagram of crc circuit aaaaaaaaaa aaaaaaaaaa crc code generating circt x 16 + x 12 + x 5 + 1 eight low-order bits aaaaa eight high-order bits data bus high-order bits data bus low-order bits aaaaaaaaaa aaaaaaaaaa aaaaaa aaaaaa crc data register (16) crc input register (8) (addresses 03bd 16 , 03bc 16 ) (address 03be 16 ) symbol address when reset crcd 03bd 16 , 03bc 16 indeterminate b7 b0 b7 b0 (b15) (b8) crc data register w r crc calculation result output register function values that can be set 0000 16 to ffff 16 symbo address when reset crcin 03be 16 indeterminate b7 b0 crc input register w r data input register function values that can be set 00 16 to ff 16
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer crc calculation circuit 127 figure uc-3. calculation example using the crc calculation circuit b15 b0 (1) setting 0000 16 crc data register crcd [03bd 16 , 03bc 16 ] b0 b7 b15 b0 (2) setting 01 16 crc input register crcin [03be 16 ] 2 cycles after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 1189 16 stores crc code b0 b7 b15 b0 (3) setting 23 16 crc input register crcin [03be 16 ] after crc calculation is complete crc data register crcd [03bd 16 , 03bc 16 ] 0a41 16 stores crc code the code resulting from sending 01 16 in lsb first mode is (1000 0000). thus the crc code in the generating polynomial, (x 16 + x 12 + x 5 + 1), becomes the remainder resulting from dividing (1000 0000) x 16 by (1 0001 0000 0010 0001) in conformity with the modulo-2 operation. thus the crc code becomes (1001 0001 1000 1000). since the operation is in lsb first mode, the (1001 0001 1000 1000) corresponds to 1189 16 in hexadecimal notation. if the crc operation in msb first mode is necessary in the crc operation circuit built in the m16c, switch between the lsb side and the msb side of the input-holding bits, and carry out the crc operation. also switch between the msb and lsb of the result as stored in crc data. 1 0001 0000 0010 0001 1000 0000 0000 0000 0000 0000 1000 1000 0001 0000 1 1000 0001 0000 1000 0 1000 1000 0001 0000 1 1001 0001 1000 1000 1000 1000 lsb msb lsb msb 98 1 1 modulo-2 operation is operation that complies with the law given below. 0 + 0 = 0 0 + 1 = 1 1 + 0 = 1 1 + 1 = 0 -1 = 1
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer programmable i/o ports 128 programmable i/o ports there are 48 programmable i/o ports: p3, p4 and p7 to p10. each port can be set independently for input or output using the direction register. a pull-up resistance for each block of 4 ports can be set. p3 and p4 0 to p4 3 are high-breakdown-voltage, p-channel open drain outputs, and have no built-in pull- down resistance (note). figures ua-1, ua-2 show the programmable i/o ports. each pin functions as a programmable i/o port and as the i/o for the built-in peripheral devices. to use the pins as the inputs for the built-in peripheral devices, set the direction register of each pin to input mode. when the pins are used as the outputs for the built-in peripheral devices (other than the d-a con- verter), they function as outputs regardless of the contents of the direction registers. when pins are to be used as the outputs for the d-a converter, do not set the direction registers to output mode. see the descriptions of the respective functions for how to set up the built-in peripheral devices. note: these ports can be selected whether pull-down resistors are built-in or not by the option specify. (1) direction registers figure ua-3 shows the direction registers. these registers are used to choose the direction of the programmable i/o ports. each bit in these regis- ters corresponds one for one to each i/o pin. (2) port registers figure ua-4 shows the port registers. these registers are used to write and read data for input and output to and from an external device. a port register consists of a port latch to hold output data and a circuit to read the status of a pin. each bit in port registers corresponds one for one to each i/o pin. (3) pull-up control registers figure ua-5 shows the pull-up control registers. the pull-up control register can be set to apply a pull-up resistance to each block of 4 ports. when ports are set to have a pull-up resistance, the pull-up resistance is connected only when the direction register is set for input. note: p3, p4 0 to p4 3 have no built-in pull-up resistance, because of these pin's are high-breakdown- voltage, p-channel open drain outputs. exclusive high-breakdown-voltage output ports there are 40 exclusive output ports: p0 to p2, p5 and p6. all ports have structure of high-breakdown-voltage p-channel open drain output. exclusive output ports except p2 have built-in pull-down resistance. figure ua-1 shows the configuration of the exclusive high-breakdown-voltage output ports.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer programmable i/o ports 129 figure ua-1. programmable i/o ports (1) p7 0 to p7 2 , p8 0 to p8 5 , p8 7 , p9 3 (inside dotted-line included) p8 6 (inside dotted-line not included) p3 0 to p3 7 , p4 0 to p4 3 p4 4 , p9 2 ,p9 4 data bus pull-up selection data bus data bus data bus pull-up selection output ? output ? input to respective peripheral functions direction register port latch port latch port latch direction register port latch direction register p0 0 to p0 7 , p1 0 to p1 7 , p5 0 to p5 7 , p6 0 to p6 7 , (inside dotted-line included) p2 0 to p2 7 (inside dotted-line not included) output v ee
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer programmable i/o ports 130 figure ua-2. programmable i/o ports (2) p4 5 to p4 7 , p7 3 to p7 7 p9 0 , p9 1 , p9 5 p9 6 (inside dotted-line included) p9 7 (inside dotted-line not included) data bus pull-up selection data bus direction register port latch pull-up selection analog output d-a output enabled direction register port latch output ? output ? p10 0 to p10 7 data bus pull-up selection direction register port latch analog input input to respective peripheral functions input to respective peripheral functions
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer programmable i/o ports 131 figure ua-3. direction register p o r t p i d i r e c t i o n r e g i s t e r s y m b o la d d r e s s w h e n r e s e t p d i ( i = 3 t o 1 0 , e x c e p t 5 , 6 )0 3 e 7 1 6 , 0 3 e a 1 6 , 0 3 e f 1 6 00 1 6 0 3 f 2 1 6 , 0 3 f 3 1 6 , 0 3 f 6 1 6 00 1 6 b i t n a m ef u n c t i o n b i t s y m b o lw r b 7b 6b 5b 4b 3b 2b 1b 0 p d i _ 0p o r t p i 0 d i r e c t i o n r e g i s t e r p d i _ 1p o r t p i 1 d i r e c t i o n r e g i s t e r p d i _ 2p o r t p i 2 d i r e c t i o n r e g i s t e r p d i _ 3p o r t p i 3 d i r e c t i o n r e g i s t e r p d i _ 4p o r t p i 4 d i r e c t i o n r e g i s t e r p d i _ 5p o r t p i 5 d i r e c t i o n r e g i s t e r p d i _ 6p o r t p i 6 d i r e c t i o n r e g i s t e r p d i _ 7p o r t p i 7 d i r e c t i o n r e g i s t e r 0 : i n p u t m o d e ( f u n c t i o n s a s a n i n p u t p o r t ) 1 : o u t p u t m o d e ( f u n c t i o n s a s a n o u t p u t p o r t ) ( i = 3 t o 1 0 e x c e p t 5 , 6 ) port pi register symbol addres when reset pi (i = 0 to 10) 03e0 16 , 03e1 16 , 03e4 16 , 03e5 16 , 03e8 16 indeterminate 03e9 16 , 03ec 16 , 03ed 16 , 03f0 16 , 03f1 16 , 03f4 16 indeterminate bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pi_0 port pi 0 register pi_1 port pi 1 register pi_2 port pi 2 register pi_3 port pi 3 register pi_4 port pi 4 register pi_5 port pi 5 register pi_6 port pi 6 register pi_7 port pi 7 register data is input and output to and from each pin by reading and writing to and from each corresponding bit 0 : ??level data 1 : ??level data (i = 0 to 10) figure ua-4. port register
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer programmable i/o ports 132 figure ua-5. pull-up control register pull-up control register 0 symbol address when rese t pur0 03fd 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu01 p4 4 to p4 7 pull-up pu06 p7 0 to p7 3 pull-up pu07 p7 4 to p7 7 pull-up pull-up control register 1 symbol address when rese t pur1 03fe 16 00 16 bit name function bit symbol w r b7 b6 b5 b4 b3 b2 b1 b0 pu10 p8 0 to p8 3 pull-up pu11 p8 4 to p8 7 pull-up pu12 p9 0 to p9 3 pull-up pu13 p9 4 to p9 7 pull-up pu14 p10 0 to p10 3 pull-up pu15 p10 4 to p10 7 pull-up the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. nothing is assigned. in an attempt to write to these bits, write ?? the value, if read, turns out to be indeterminate. the corresponding port is pulled high with a pull-up resistor 0 : not pulled high 1 : pulled high nothing is assigned. in an attempt to write to this bit, write ?? the value, if read, turns out to be indeterminate.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer programmable i/o ports 133 table ua-1. example connection of unused pins figure ua-6. example connection of unused pins pin name connection ports p3, p4(note 2), p7 to p10 specify output mode, and leave these pins open; or specify input mode, and connect to v ss via resistor (pull-down) note 1: with external clock input to x in pin. note 2: in case of pull-down option is specified, leave the specified ports open. (pull-down resistors are built-in the specified port) note 3: connect a bypass capacitor. x out (note 1), v ee av ss , v ref av cc open connect to v cc (note 3) connect to v ss (note 3) ports p0 to p2, p5, p6 leave these pins open cnv ss connect to v ss via resistor port p3, p4(note 1), p7 to p10 (input mode) (output mode) port p0 to p2, p5, p6 (output mode) x out av cc (note 2) cnv ss av ss (note 2) v ref (note 2) microcomputer v cc v ss open open open v ee open note 1: in case of pull-down option is specified, leave the specified ports (port p3, p4) open. (pull-down resistors are built-in the specified port) note 2: connect a bypass capacitor.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer pull-down 134 mask option of pull-down resistor (object product: mask rom version) whether built-in pull-down resistors are connected or not to high-breakdown voltage ports p2 0 to p2 7 , p3 0 to p3 7 ,and p4 0 to p4 3 can be specified in ordering mask rom. the option type can be specified from among 7 types; a to g. a b c d e f g p2 0 p2 1 p2 2 p2 3 p2 4 p2 5 p2 6 p2 7 p3 0 p3 1 p3 2 p3 3 p3 4 p3 5 p3 6 p3 7 p4 0 p4 1 p4 2 0000000000000000000 p4 3 0 1111000000000000000 0 1111111100000000000 0 1111111111110000000 0 1111111111111111000 0 1111111111111111110 0 1111111111111111111 1 note 1: the electrical characteristics of high-breakdown voltage ports p2 0 to p2 7 , p3 0 to p3 7 ,and p4 0 to p4 3 s built-in pull-down resistors are the same as that of high-breakdown voltage ports p0 0 to p0 7 . note 2: the absolute maximum ratings of power dissipation may be exceed owing to the number of built-in pull-down resistor. after calculating the power dissipation, specify the option type. note 3: the option types b to g cannot be specified because these types are currently under development. power dissipation calculating method (fixed number depending on microcomputers standard) ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value = 68 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v x 38 ma = 190 mw ( fixed number depending on use condition) ? apply voltage to v ee pin: vcc C 50 v ? timing number a; digit number b; segment number c ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: d ? all segment number during repeat cycle: e (= a x c) ? total number of built-in resistor: for digit; f, for segment; g ? digit pin current value h (ma) ? segment pin current value i (ma) (1) digit pin power dissipation {h x b x (1Ctoff / tdisp) x voltage} / a (2) segment pin power dissipation {i x d x (1Ctoff / tdisp) x voltage} / a (3) pull-down resistor power dissipation (digit) {power dissipation per 1 digit x (b x f / b) x (1Ctoff / tdisp) } / a (4) pull-down resistor power dissipation (segment) {power dissipation per 1 segment x (d x g / c) x (1Ctoff / tdisp) } / a (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190 mw (1) + (2)+ (3) + (4) + (5) = x mw
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer pull-down 135 power dissipation calculating example 1 fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 68 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v x 38 ma = 190 mw fixed number depending on use condition ? apply voltage to v ee pin: vcc C 50 v ? timing number 17; digit number 16; segment number 20 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 31 ? all segment number during repeat cycle: 340 (= 17 x 20) ? total number of built-in resistor: for digit; 16, for segment; 20 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation {18 x 16 x (1C1/16) x 2} / 17 = 31.77 mw (2) segment pin power dissipation {3 x 31 x (1C1/16) x 2} / 17 = 10.26 mw (3) pull-down resistor power dissipation (digit) (50 C 2) 2 /68 x (16 x 16/16) x (1 C 1/16) / 17 = 29.90 mw (4) pull-down resistor power dissipation (segment) (50 C 2) 2 /68 x (31 x 20/20) x (1 C 1/16) / 17 = 57.93 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190.00 mw (1) + (2)+ (3) + (4) + (5) = 319.86 mw dig0 dig1 dig2 dig3 dig13 dig14 dig15 timing number 12 3 16 17 15 14 tscan repeat cycle figure s-1. digit timing waveform (1)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer pull-down 136 power dissipation calculating example 2(when 2 or more digit is turned on at same time) fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 68 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v x 38 ma = 190 mw fixed number depending on use condition ? apply voltage to v ee pin: vcc C 50 v ? timing number 11; digit number 12; segment number 24 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 114 ? all segment number during repeat cycle: 264 (= 11 x 24) ? total number of built-in resistor: for digit; 10, for segment; 22 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation {18 x 12 x (1C1 / 16) x 2} / 11 = 36.82 mw (2) segment pin power dissipation {3 x 114 x (1C1 / 16) x 2} / 11 = 58.30 mw (3) pull-down resistor power dissipation (digit) (50C 2) 2 / 68 x (12 x 10 / 12) x (1 C 1 / 16) / 11 = 28.88 mw (4) pull-down resistor power dissipation (segment) (50 C 2) 2 / 68 x (114 x 22 / 24) x (1 C 1 / 16) / 11 = 301.77 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190.00 mw (1) + (2)+ (3) + (4) + (5) = 615.77 mw (there is a limit of use temperature) dig0 dig1 dig2 dig3 dig7 dig8 dig9 timing number 12 3 45 6 7 89 1011 dig4 dig5 dig6 tscan repeat cycle figure s-2. digit timing waveform (2)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer pull-down 137 power dissipation calculating example 3 (when 2 or more digit is turned on at same time, and used toff invalid function) fixed number depending on microcomputers standard ? v oh output fall voltage of high-breakdown port 2 v (max.); | current value | = at 18 ma ? resistor value 68 k w (min.) ? power dissipation of internal circuit (cpu, rom, ram etc.) = 5 v x 38 ma = 190 mw fixed number depending on use condition ? apply voltage to v ee pin: vcc C 50 v ? timing number 11; digit number 12; segment number 24 ? ratio of toff time corresponding tdisp time: 1/16 ? turn on segment number during repeat cycle: 114 ( for toff invalid waveform;50) ? all segment number during repeat cycle: 264 (= 11 x 24) ? total number of built-in resistor: for digit; 10, for segment; 22 ? digit pin current value: 18 (ma) ? segment pin current value: 3 (ma) (1) digit pin power dissipation [{18 x 10 x (1C1/16) x 2} + {18 x 2 x 2}] / 11 = 37.23 mw (2) segment pin power dissipation [{3 x 64 x (1C1/16) x 2} + {3 x 50 x 2}] / 11 = 60.00 mw (3) pull-down resistor power dissipation (digit) [{(50C 2) 2 / 68 x (10 x 10 / 12) x (1 C 1 / 16)} + {(50C 2) 2 / 68 x (2 x 10 / 12) } ] /11 = 29.20 mw (4) pull-down resistor power dissipation (segment) [{(50C 2) 2 / 68 x (64 x 22 / 24) x (1 C 1 / 16)} + {(50C 2) 2 / 68 x (50 x 22 / 24) } ] / 11 = 310.59 mw (5) internal circuit power dissipation (cpu, rom, ram etc.) = 190.00 mw (1) + (2)+ (3) + (4) + (5) = 627.02 mw (there is a limit of use temperature) figure s-3. digit timing waveform (3) dig0 dig1 dig2 dig3 dig7 dig8 dig9 timing number 12 3 45 6 7 89 1011 dig4 dig5 dig6 tscan repeat cycle
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer electrical characteristics 138 table z-1. absolute maximum ratings operating ambient temperature parameter unit v ref, x in input voltage reset , cnvss , analog supply voltage supply voltage output voltage v o - 0.3 to vcc+0.3 (note) p d storage temperature - 0.3 to 6.5 standard - 0.3 to 6.5 v v v condition v i avcc vcc t stg t opr symbol v -40 to 150 -20 to 85 p4 4 to p4 7, p7 0 to p7 7, p8 0 to p8 7, p9 0 to p9 7, p10 0 to p10 7, 2.7(note1) 5.5 typ. max. unit parameter vcc 5.0 supply voltage symbol min standard analog supply voltage vcc avcc v v 0 0 analog supply voltage supply voltage vss avss 0.8vcc v v v v 0.52vcc vcc vcc 0.16vcc 0 high input voltage low input voltage high input voltage p3 0 to p3 7, p4 0 to p4 3 v p3 0 to p3 7, p4 0 to p4 3 p7 0 to p7 7, p8 0 to p8 7, p9 0 to p9 7, p10 0 to p10 7, x in, reset , cnv ss v ih v ih v il pull-down supply voltage vcc - 50 to vcc+0.3v v v ee v i p3 0 to p3 7, p4 0 to p4 3 input voltage vcc - 50 to vcc+0.3 v p0 0 to p0 7, p1 0 to p1 7, p2 0 to p2 7, p3 0 to p3 7, p4 0 to p4 3, p5 0 to p5 7, output voltage v o p6 0 to p6 7 vcc - 50 to vcc+0.3 v v ee pull-down supply voltage vcc-48 vcc v v il low input voltage p7 0 to p7 7, p8 0 to p8 7, p9 0 to p9 7, p10 0 to p10 7, x in, reset , cnv ss 0 v 0.2vcc x out p4 4 to p4 7, p7 0 to p7 7, p8 0 to p8 7, p9 0 to p9 7, p10 0 to p10 7, -0.3 to vcc+0.3 power dissipation ta=-20 to 60 750 750-12 x (ta-60) ta=60 to 85 mw mw v ih p4 4 to p4 7 0.50vcc vcc v high input voltage v 0.16vcc 0 low input voltage p4 4 to p4 7 v il c c c c note 1: when writing to flash ,only cnvss is C0.3 to 13 (v) . note: v cc = 4.0v to 5.5v in flash memory version. table z-2. recommended operating conditions (referenced to v cc = 2.7v to 5.5v at ta = C 20 to 85 o c unless otherwise specified) (note)
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer electrical characteristics 139 table z-3. recommended operating conditions (referenced to v cc = 2.7v to 5.5v at ta = C 20 to 85 o c unless otherwise specified) (note 6) note 1: the total output current is the sum of all the currents through the applicable ports. the total average value measured over 100ms. the total peak current is the peak of all the currents. note 2: the peak output current is the peak current flowing in each port. note 3: the average output current in an average value measured over 100ms. note 4: when the oscillating frequency has a duty cycle of 50 %. note 5: when using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(x cin ) < f(x in ) / 3. note 6: v cc =4.0v to 5.5v in flash memory version. note 7: relationship between main clock oscillation frequency and supply voltage. aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaaaaaa aaa a a a a a a a a a a a a a a a aaa 10.0 3.5 0.0 2.7 4.0 5.5 main clock input oscillation frequency (no wait) 5 x v cc -10.000mh z flash memory version operating maximum frequency [mh z ] supply voltage [v] (bclk: no division) i oh (avg) ma ma i oh (peak) -18 -40 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 f (x in ) mhz 10 f (xc in ) khz 50 32.768 vcc=4.0v to 5.5v vcc=2.7v to 4.0v mhz 0 0 5 x vcc-10 symbol parameter unit standard min typ. max. high peak output current (note 2) high average output current (note 3) main clock input oscillation frequency (note 4, 7) sub clock oscillation frequency (note 4, 5) p0 0 to p0 7 , p5 0 to p5 7 , p6 0 to p6 7 high total peak output current (note 1) i oh (peak) -240 ma p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 3 high total peak output current (note 1) i oh (peak) -240 ma p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 5 high total peak output current (note 1) i oh (peak) -80 ma p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 high total peak output current (note 1) i oh (peak) -80 ma p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 5 low total peak output current (note 1) i ol (peak) 80 ma p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 low total peak output current (note 1) i ol (peak) 80 ma p0 0 to p0 7 , p5 0 to p5 7 , p6 0 to p6 7 high total average output current (note 1) i oh (avg) -120 ma p1 0 to p1 7 , p2 0 to p2 7 , p3 0 to p3 7 , p4 0 to p4 3 high total average output current (note 1) i oh (avg) -120 ma p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 5 high total average output current (note 1) i oh (avg) -40 ma p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 high total average output current (note 1) i oh (avg) -40 ma p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 5 low total average output current (note 1) i ol (avg) 40 ma p8 6 , p8 7 , p9 0 to p9 7 , p10 0 to p10 7 low total average output current (note 1) i ol (avg) 40 ma ma i oh (peak) -10 p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 7 high peak output current (note 2) p9 0 to p9 7 , p10 0 to p10 7 ma i ol (peak) 10 p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 7 low peak output current (note 2) p9 0 to p9 7 , p10 0 to p10 7 p0 0 to p0 7 , p1 0 to p1 7 , p2 0 to p2 7 ,p3 0 to p3 7 , p4 0 to p4 3 , p5 0 to p5 7 , p6 0 to p6 7 i oh (avg) ma -5 high average output current (note 3) p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 7 p9 0 to p9 7 , p10 0 to p10 7 i ol (avg) ma 5 low average output current (note 3) p4 4 to p4 7 , p7 0 to p7 7 , p8 0 to p8 7 p9 0 to p9 7 , p10 0 to p10 7
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer electrical characteristics (v cc =5v) v cc =5v 140 table z-4. electrical characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c, f(x in ) =10mh z unless otherwise specified) x i n , r e s e t , c n v s s s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e l o w i n p u t c u r r e n t i i l h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n v v v x o u t 3 . 0 3 . 0 v 2 . 0 m a m i n .m a x . 3 . 5 p a r a m e t e r i o h = - 1 8 m a i o h = - 1 m a i o h = - 5 m a i o h = - 0 . 5 m a i o l = 5 m a p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 v i = 0 v - 5 . 0 h i g h p o w e r l o w p o w e r l o w o u t p u t v o l t a g e v o l h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i i h v t + - v t - v t + - v t - v x o u t 2 . 0 2 . 0 0 . 20 . 8v 0 . 21 . 8v 5 . 0 m a i o l = 1 m a i o l = 0 . 5 m a r e s e t p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , v i = 5 v h i g h p o w e r l o w p o w e r p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , c l k 0 , c l k 1 , s r d y 2 i n , s b s y 2 i n , i n t 0 t o i n t 5 , c t s 0 , c t s 1 , s i n 2 , s c l k 2 1 , s c l k 2 2 , r x d 0 , i i h p 3 0 t o p 3 7 , p 4 0 t o p 4 3 ( n o t e 1 ) v i = 5 v 5 . 0 m a i i l p 3 0 t o p 3 7 , p 4 0 t o p 4 3 ( n o t e 1 ) v i = 0 v - 5 . 0 m a r p u l l u p p u l l - u p r e s i s t a n c e p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , i o h = - 5 m a 4 . 5 3 0 . 05 0 . 01 6 7 . 0 k w 3 . 0 r x d 1 r f x i n f e e d b a c k r e s i s t a n c e x i n 1 . 0 r p u l l d p u l l - d o w n r e s i s t a n c e p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 v e e = v c c - 4 8 v , v o l = v c c o u t p u t t r a n s i s t o r s o f f i l e a k o u t p u t l e a k c u r r e n t p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 4 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 v e e = v c c - 4 8 v , v o l = v c c - 4 8 v o u t p u t t r a n s i s t o r s o f f 6 88 01 2 0 k w (p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3 i n o p t i o n s p e c i f y ) - 1 0 m a v i = 0 v v r a m r a m r e t e n t i o n v o l t a g e i c cp o w e r s u p p l y c u r r e n t ( n o t e 3 ) w h e n c l o c k i s s t o p p e d2 . 0v s q u a r e w a v e , n o d i v i s i o n 1 . 0 m a m a 2 0 . 0 1 9 . 03 8 . 0 f ( x i n ) = 1 0 m h z f ( x c i n ) = 3 2 k h z 4 . 0 m a s q u a r e w a v e , 8 d i v i s i o n f ( x i n ) = 1 0 m h z 4 . 2m a s q u a r e w a v e ( n o t e 2 ) f ( x c i n ) = 3 2 k h z 9 0 . 0 m a m w r f x c i n f e e d b a c k r e s i s t a n c e x c i n 6 . 0 m w th e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s w h e n a w a i t i n s t r u c t i o n i s e x e c u t e d ( n o t e 2 ) t a = 8 5 w h e n c l o c k i s s t o p p e d t a = 2 5 w h e n c l o c k i s s t o p p e d c c note 1: except when reading ports p3, p4 0 to p4 3 . note 2: fixed x cin -x cout drive capacity select bit to high and x in pin to h level. note 3: this contains an electric current to flow into av cc pin.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer electrical characteristics (v cc =5v) v cc =5v 141 table z-5. a-d conversion characteristics (referenced to v cc = av cc = v ref = 5v, vss = av ss = 0v at ta = 25 o c, f(x in ) = 10mh z unless otherwise specified) table z-6. d-a conversion characteristics (referenced to v cc = 5v, v ss = av ss = 0v, v ref = 5v at ta = 25 o c, f(x in ) = 10mh z unless otherwise specified) m s standard min. typ. max. resolution absolute accuracy bits lsb v ref = v cc 3 10 symbol parameter measuring condition unit v ref = v cc = 5v r ladder t conv ladder resistance conversion time (10bit) reference voltage analog input voltage k w v v ia v ref v 0 2 10 v cc v ref 40 3.3 conversion time (8bit) 2.8 t conv t samp sampling time 0.3 v ref = v cc sample & hold function not available sample & hold function available(10bit) an 0 to an 7 input v ref =v cc = 5v lsb sample & hold function available(8bit) v ref = v cc = 5v 2 lsb m s m s 3 min. typ. max. t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % k w ma i vref 1.0 1.5 8 3 symbol parameter measuring condition unit 20 10 4 m s ( note ) standard note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the vref is unconnected at the a-d control register, i vref is sent.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timing (v cc =5v) v cc =5v 142 timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table z-7. external clock input max. external clock rise time ns t r min. external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time ns ns ns ns t c t w(h ) t w(l) t f parameter symbol unit standard 15 100 40 40 15 switching characteristics (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table z-8. high-breakdown voltage p-channel open-drain output port symbol standard measuring condition max. typ. parameter unit min. t r(pch-strg) p-channel high-breakdown voltage output rising time (note 1) 55 ? ns t r(pch-weak) p-channel high-breakdown voltage output rising time (note 2) 1.8 c l =100pf v ee =v cc - 43v c l =100pf v ee =v cc - 43v note 1: when bit 7 of the fldc mode register (address 0350 16 ) is at ?? note 2: when bit 7 of the fldc mode re g ister ( address 0350 16 ) is at ?? v ee p0, p1, p2, p3, p4 0 to p4 3 , p5, p6 p-channel high- breakdown voltage output port (note) note: ports p2, p3, and p4 0 to p4 3 need external resistors in mask rom version. (in case of not mask option specified) ports p2, p3, and p4 0 to p4 3 need external resistors in flash memory version. c l figure z-2. circuit for measuring output switching characteristics
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timing (v cc =5v) v cc =5v 143 timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table z-9. timer a input (counter input in event counter mode) table z-10. timer a input (gating input in timer mode) table z-11. timer a input (external trigger input in one-shot timer mode) table z-12. timer a input (external trigger input in pulse width modulation mode) table z-13. timer a input (up/down input in event counter mode) standard max. ns tai in input low pulse width t w(tal) min. ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns ns unit standard max. min. ns ns unit standard max. min. ns ns ns unit ns ns tai in input high pulse width t w(tah) parameter symbol tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter tai in input cycle time tai in input high pulse width tai in input low pulse width t c(ta) t w(tah) t w(tal) symbol parameter t w(tah) t w(tal) symbol parameter tai in input high pulse width tai in input low pulse width symbol parameter t c(ta) tai in input cycle time tai out input cycle time tai out input high pulse width tai out input low pulse width tai out input setup time tai out input hold time t c(up) t w(uph) t w(upl) t su(up-t in ) t h(t in- up) 40 100 40 400 200 200 200 100 100 100 100 2000 1000 1000 400 400
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timing (v cc =5v) v cc =5v 144 table z-15. timer b input (pulse period measurement mode) timing requirements (referenced to v cc = 5v, v ss = 0v at ta = 25 o c unless otherwise specified) table z-14. timer b input (counter input in event counter mode) ns ns ns ns ns ns ns standard max. min. tbi in input cycle time (counted on one edge) tbi in input high pulse width (counted on one edge) tbi in input low pulse width (counted on one edge) ns ns ns t c(tb) t w(tbh) t w(tbl) parameter symbol unit t c(tb) t w(tbl) t w(tbh) ns ns ns tbi in input high pulse width (counted on both edges) tbi in input low pulse width (counted on both edges) tbi in input cycle time (counted on both edges) standard max. min. ns ns t c(tb) t w(tbh) symbol parameter unit t w(tbl) ns tbi in input high pulse width tbi in input cycle time tbi in input low pulse width standard max. min. ns ns t c(tb) symbol parameter unit t w(tbl) ns t w(tbh) tbi in input cycle time tbi in input high pulse width tbi in input low pulse width standard max. min. ns ns t w(inh) t w(inl) symbol parameter unit inti input low pulse width inti input high pulse width standard max. min. clki input cycle time clki input high pulse width clki input low pulse width t c(ck) t w(ckh) t w(ckl) parameter symbol unit t d(c-q) t su(d-c) t h(c-q) txdi hold time rxdi input setup time txdi output delay time t h(c-d) rxdi input hold time 100 40 40 80 80 200 400 200 200 400 200 200 250 250 200 100 100 0 30 90 80 ? ns ns ns standard max. min. serial i/o clock input cycle time serial i/o clock input high pulse width serial i/o clock input low pulse width t c(sclk) t wh(sclk) t wl(sclk) parameter symbol unit t su(sclk-sin) serial i/o input setup time t h(sclk-sin) serial i/o input hold time 0.95 400 200 200 ns 400 table z-16. timer b input (pulse width measurement mode) table z-17. serial i/o _______ table z-18. external interrupt inti inputs table z-19. automatic transfer serial i/o
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timing (v cc =5v) v cc =5v 145 t su(d-c) tai in input tai out input during event counter mode tbi in input clk i txd i rxd i t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) t h(t in -up) t su(up-t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) s out s in s clk 0.2v cc t d(sclk-sout) 0.2v cc 0.8v cc 0.8v cc t su(sin-sclk) t h(sclk-sin) t v(sclk-sout) t wl(sclk) t wh(sclk) tf (sclk) t c(sclk) t r
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer electrical characteristics(v cc =3v, only mask rom version) v cc =3v 146 table z-20. electrical characteristics (referenced to v cc = 3v, v ss = 0v at ta = 25 o c, f(x in ) =5mh z unless otherwise specified) x i n , r e s e t , c n v s s s y m b o l v o h v o h h i g h o u t p u t v o l t a g e v o h v o l l o w o u t p u t v o l t a g e l o w i n p u t c u r r e n t i i l h i g h o u t p u t v o l t a g e h i g h o u t p u t v o l t a g e s t a n d a r d t y p . u n i t m e a s u r i n g c o n d i t i o n v v v x o u t 2 . 5 2 . 5 v 0 . 5 m a m i n .m a x . 1 . 5 p a r a m e t e r i o h = - 1 8 m a i o h = - 0 . 1 m a i o h = - 1 m a i o h = - 5 0 m a i o l = 1 m a p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 v i = 0 v - 4 . 0 h i g h p o w e r l o w p o w e r l o w o u t p u t v o l t a g e v o l h y s t e r e s i s h y s t e r e s i s h i g h i n p u t c u r r e n t i i h v t + - v t - v t + - v t - v x o u t 0 . 5 0 . 5 0 . 20 . 8v 0 . 21 . 8v 4 . 0 m a i o l = 0 . 1 m a i o l = 5 0 m a r e s e t p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , v i = 3 v h i g h p o w e r l o w p o w e r p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 t a 0 i n t o t a 4 i n , t b 0 i n t o t b 2 i n , c l k 0 , c l k 1 , s r d y 2 i n , s b s y 2 i n , i n t 0 t o i n t 5 , c t s 0 , c t s 1 , s i n 2 , s c l k 2 1 , s c l k 2 2 i i h p 3 0 t o p 3 7 , p 4 0 t o p 4 3 ( n o t e 1 ) v i = 3 v 4 . 0 m a i i l p 3 0 t o p 3 7 , p 4 0 t o p 4 3 ( n o t e 1 ) v i = 0 v - 4 . 0 m a r p u l l u p p u l l - u p r e s i s t a n c e p 4 4 t o p 4 7 , p 7 0 t o p 7 7 , p 8 0 t o p 8 7 , p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , x i n , r e s e t , c n v s s p 9 0 t o p 9 7 , p 1 0 0 t o p 1 0 7 , i o h = - 5 m a 2 . 5 6 6 . 01 2 0 . 05 0 0 . 0 k w 2 . 5 r t s 0 , r t s 1 r f x i n f e e d b a c k r e s i s t a n c e x i n 3 . 0 r p u l l d p u l l - d o w n r e s i s t a n c e p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 v e e = v c c - 4 8 v , v o l = v c c o u t p u t t r a n s i s t o r s o f f i l e a k o u t p u t l e a k c u r r e n t p 0 0 t o p 0 7 , p 1 0 t o p 1 7 , p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 4 , p 5 0 t o p 5 7 , p 6 0 t o p 6 7 v e e = v c c - 4 8 v , v o l = v c c - 4 8 v o u t p u t t r a n s i s t o r s o f f 6 88 01 2 0 k w ( p 2 0 t o p 2 7 , p 3 0 t o p 3 7 , p 4 0 t o p 4 3 i n o p t i o n s p e c i f y ) - 1 0 m a v i = 0 v v r a m r a m r e t e n t i o n v o l t a g e i c cp o w e r s u p p l y c u r r e n t ( n o t e 3 ) w h e n c l o c k i s s t o p p e d2 . 0v s q u a r e w a v e , n o d i v i s i o n 1 . 0 m a m a 2 0 . 0 t h e o u t p u t p i n s a r e o p e n a n d o t h e r p i n s a r e v s s 6 . 01 5 . 0 f ( x i n ) = 5 m h z f ( x c i n ) = 3 2 k h z 2 . 8 m a s q u a r e w a v e , 8 d i v i s i o n f ( x i n ) = 5 m h z 1 . 6m a f ( x c i n ) = 3 2 k h z 0 . 9 m a m w r f x c i n f e e d b a c k r e s i s t a n c e x c i n 1 0 . 0 m w s q u a r e w a v e f ( x c i n ) = 3 2 k h z 5 0 . 0 m a t a = 8 5 w h e n c l o c k i s s t o p p e d t a = 2 5 w h e n c l o c k i s s t o p p e d c c w h e n a w a i t i n s t r u c t i o n i s e x e c u t e d . o s c i l l a t i o n c a p a c i t y h i g h ( n o t e 2 ) w h e n a w a i t i n s t r u c t i o n i s e x e c u t e d . o s c i l l a t i o n c a p a c i t y l o w ( n o t e 2 ) note 1: except when reading ports p3, p4 0 to p4 3 . note 2: with one timer operated using f c32 . note 3: this contains an electric current to flow into av cc pin.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer electrical characteristics(v cc =3v, only mask rom version) v cc =3v 147 table z-21. a-d conversion characteristics (referenced to v cc = av cc = v ref = 3v, vss = av ss = 0v at ta = 25 o c, f(x in ) = 5mh z unless otherwise specified) table z-22. d-a conversion characteristics (referenced to v cc = 3v, v ss = av ss = 0v, v ref = 3v at ta = 25 o c, f(x in ) = 5mh z unless otherwise specified) r ladder ladder resistance reference voltage analog input voltage v v ia v ref v 0 2.7 10 v cc v ref 40 conversion time (8bit) 14.0 t conv v ref = v cc standard min. typ. max resolution absolute accuracy bits lsb v ref = v cc 2 10 symbol parameter measuring condition unit v ref = v cc = 3v, f ad = f(x in )/2 sample & hold function not available (8 bit) k w m s standard min. typ. max t su r o resolution absolute accuracy setup time output resistance reference power supply input current bits % ma i vref 1.0 1.0 8 3 symbol parameter measuring condition unit 20 10 4 (note) k w m s note: this applies when using one d-a converter, with the d-a register for the unused d-a converter set to 00 16 . the a-d converter's ladder resistance is not included. also, when the vref is unconnected at the a-d control register, i vref is sent.
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timing(v cc =3v, only mask rom version) v cc =3v 148 timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table z-23. external clock input ns ns ns ns ns t c t w(h ) t w(l) t r t f max. min. parameter symbol unit standard external clock rise time external clock input cycle time external clock input high pulse width external clock input low pulse width external clock fall time 200 85 85 18 18
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timing(v cc =3v, only mask rom version) v cc =3v 149 timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table z-24. timer a input (counter input in event counter mode) table z-25. timer a input (gating input in timer mode) table z-26. timer a input (external trigger input in one-shot timer mode) table z-27. timer a input (external trigger input in pulse width modulation mode) table z-28. timer a input (up/down input in event counter mode) standard max. min. unit parameter symbol ns t w(tal) tai in input low pulse width 60 ns t c(ta) tai in input cycle time 150 ns t w(tah) tai in input high pulse width 60 standard max. min. unit parameter symbol ns t c(ta) tai in input cycle time 600 ns t w(tah) tai in input high pulse width 300 ns t w(tal) tai in input low pulse width 300 standard max. min. unit parameter symbol ns t c(ta) tai in input cycle time 300 ns t w(tah) tai in input high pulse width 150 ns t w(tal) tai in input low pulse width 150 standard max. min. unit parameter symbol ns t w(tah) tai in input high pulse width 150 ns t w(tal) tai in input low pulse width 150 standard max. min. unit parameter symbol ns t c(up) tai out input cycle time 3000 ns t w(uph) tai out input high pulse width 1500 ns t w(upl) tai out input low pulse width 1500 ns t su(up-t in ) tai out input setup time 600 ns t h(t in- up) tai out input hold time 600
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timing(v cc =3v, only mask rom version) v cc =3v 150 table z-30. timer b input (pulse period measurement mode) timing requirements (referenced to v cc = 3v, v ss = 0v at ta = 25 o c unless otherwise specified) table z-29. timer b input (counter input in event counter mode) table z-31. timer b input (pulse width measurement mode) table z-32. serial i/o _______ table z-33. external interrupt inti inputs table z-34. automatic transfer serial i/o standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time (counted on one edge) 150 ns t w(tbh) tbi in input high pulse width (counted on one edge) 60 ns t w(tbl) tbi in input low pulse width (counted on one edge) 60 t w(tbh) ns tbi in input high pulse width (counted on both edges) 160 t w(tbl) ns tbi in input low pulse width (counted on both edges) 160 t c(tb) ns tbi in input cycle time (counted on both edges) 300 standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time 600 ns t w(tbh) tbi in input high pulse width 300 t w(tbl) ns tbi in input low pulse width 300 standard max. min. parameter symbol unit ns t c(tb) tbi in input cycle time 600 ns t w(tbh) tbi in input high pulse width 300 t w(tbl) ns tbi in input low pulse width 300 standard max. min. parameter symbol unit ns t w(inh) inti input high pulse width 380 ns t w(inl) inti input low pulse width 380 standard max. min. parameter symbol unit ns t c(ck) clki input cycle time 300 ns t w(ckh) clki input high pulse width 150 ns t w(ckl) clki input low pulse width 150 t h(c-q) ns txdi hold time 0 t su(d-c) ns rxdi input setup time 50 t h(c-d) ns rxdi input hold time 90 t d(c-q) ns txdi output delay time 160 ? ns ns ns standard max. min. serial i/o clock input cycle time serial i/o clock input high pulse width serial i/o clock input low pulse width t c(sclk) t wh(sclk) t wl(sclk) parameter symbol unit t su(sclk-sin) serial i/o input setup time t h(sclk-sin) serial i/o input hold time tbd ns tbd tbd tbd tbd
under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer timing(v cc =3v, only mask rom version) v cc =3v 151 t su(d-c) tai in input tai out input during event counter mode tbi in input clk i txd i rxd i t c(ta) t w(tah) t w(tal) t c(up) t w(uph) t w(upl) t c(tb) t w(tbh) t w(tbl) t c(ck) t w(ckh) t w(ckl) t w(inl) t w(inh) int i input t d(c-q) t h(c-d) t h(c-q) t h(t in -up) t su(up-t in ) tai in input (when count on falling edge is selected) tai in input (when count on rising edge is selected) tai out input (up/down input) s out s in s clk 0.2v cc t d(sclk-sout) 0.2v cc 0.8v cc 0.8v cc t su(sin-sclk) t h(sclk-sin) t v(sclk-sout) t wl(sclk) t wh(sclk) tf (sclk) t c(sclk) t r
description under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 152 item power supply voltage program/erase voltage flash memory operation mode erase block division program method erase method program/erase control method number of commands program/erase count rom code protect performance 4.0v to 5.5 v (f(x in )=10mhz) v pp =12v 5% (f(x in )=10mhz) three modes (parallel i/o, standard serial i/o, cpu rewrite) see figure 1.aa.3. one division (3.5 k bytes) (note) in units of byte collective erase / block erase program/erase control by software command 6 commands 100 times standard serial i/o mode is supported. note: the boot rom area contains a standard serial i/o mode control program which is stored in it when shipped from the factory. this area can be erased and programmed in only parallel i/o mode. user rom area boot rom area v cc =5v 10% (f(x in )=10mhz) table aa-1. outline performance of the m30218 group (flash memory version) outline performance table aa-1 shows the outline performance of the m30218 group (flash memory version).
description under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 153 flash memory the m30218 group (flash memory version) contains the nor type of flash memory that requires a high- voltage v pp power supply for program/erase operations, in addition to the v cc power supply for device operation. for this flash memory, three flash memory modes are available in which to read, program, and erase: parallel i/o and standard serial i/o modes in which the flash memory can be manipulated using a programmer and a cpu rewrite mode in which the flash memory can be manipulated by the central pro- cessing unit (cpu). each mode is detailed in the pages to follow. in addition to the ordinary user rom area to store a microcomputer operation control program, the flash memory has a boot rom area that is used to store a program to control rewriting in cpu rewrite and standard serial i/o modes. this boot rom area has had a standard serial i/o mode control program stored in it when shipped from the factory. however, the user can write a rewrite control program in this area that suits the users application system. this boot rom area can be rewritten in only parallel i/o mode. figure aa-3. block diagram of flash memory version sfr ram sfr ram sfr ram user rom area 00000 16 00400 16 yyyyy 16 df000 16 xxxxx 16 fffff 16 microcomputer mode parallel i/o mode cpu rewrite mode standard serial i/o mode boot rom area (3.5k bytes) user rom area user rom area boot rom area (3.5k bytes) dfdff 16 e0000 16 e8000 16 f0000 16 f8000 16 fffff 16 block 3 block 2 block 1 block 0 type no. xxxxx 16 yyyyy 16 m30218fc e0000 16 033ff 16 collective erasable/ programmable area collective erasable/ programmable area collective erasable/ programmable area note 1: in cpu rewrite and standard serial i/o modes, the user rom is the only erasable/programmable area. note 2: in parallel i/o mode, the area to be erased/programmed can be selected by the address a17 input. the user rom area is selected when this address input is high and the boot rom area is selected when this address input is low. index outline performance flash memory modes cpu rewrite mode outline performance (cpu rewrite mode) flash memory modes outline performance functions to inhibit rewriting on-chip flash memory parallel i/o mode standard serial i/o mode
cpu rewrite mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 154 cpu rewrite mode in cpu rewrite mode, the on-chip flash memory can be operated on (read, program, or erase) under control of the central processing unit (cpu). in cpu rewrite mode, the flash memory can be operated on by reading or writing to the flash memory control register and flash command register. figure bb-1, figure bb- 2 show the flash memory control register, and flash command register respectively. also, in cpu rewrite mode, the cnv ss pin is used as the v pp power supply pin. apply the power supply voltage, v pp h, from an external source to this pin. in cpu rewrite mode, only the user rom area shown in figure aa-3 can be rewritten; the boot rom area cannot be rewritten. make sure the program and block commands are issued for only the user rom area. the control program for cpu rewrite mode can be stored in either user rom or boot rom area. in the cpu rewrite mode, because the flash memory cannot be read from the cpu, the rewrite control program must be transferred to internal ram before it can be executed. flash memory control register 0 symbol address when reset fcon0 03b4 16 00100000 2 w r b7 b6 b5 b4 b3 b2 b1 b0 cpu rewrite mode select bit fcon00 bit symbol bit name function rw 0: cpu rewrite mode is invalid 1: cpu rewrite mode is valid this bit can not write. the value, if read, turns out to be indeterminate. reserved bit cpu rewrite mode monitor flag 0: cpu rewrite mode is invalid 1: cpu rewrite mode is valid must always be set to "0". fcon02 aa aa aa a aa a reserved bit 0 000: block 0 program/erase 001: block 1 program/erase 010: block 2 program/erase 011: block 3 program/erase 110: block 0 to 3 erase 111: inhibit 0 aa aa a a must always be set to "0". reserved bit flash memory control register 1 symbol address when reset fcon1 03b5 16 xxxxxx00 2 w r b7 b6 b5 b4 b3 b2 b1 b0 bit symbol bit name function rw 0 aa 0 reserved bit a nothing is assigned. in an attempt to write these bits, write "0". the value, if read, turns out to be indeterminate. must always be set to "0". a aa a aa a fcon04 fcon05 fcon06 b6b5b4 erase / program area select bit flash command register symbol address when reset fcmd 03b6 16 00 16 w r b7 b6 b5 b4 b3 b2 b1 b0 writing of software command read command "00 16 " program command "40 16 " program verify command "c0 16 " erase command "20 16 " + "20 16 " ?rase verify command "a0 16 " ?eset command "ff 16 " + "ff 6 " function rw a figure bb-1. flash memory control register figure bb-2. flash command register
cpu rewrite mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 155 microcomputer mode and boot mode the control program for cpu rewrite mode must be written into the user rom or boot rom area in parallel i/o mode beforehand. (if the control program is written into the boot rom area, the standard serial i/o mode becomes unusable.) see figure aa-3 for details about the boot rom area. normal microcomputer mode is entered when the microcomputer is reset with pulling cnv ss pin low (v ss ). in this case, the cpu starts operating using the control program in the user rom area. when the microcomputer is reset by pulling the p5 2 pin high (v cc ), the cnv ss pin high(v pph ), the cpu starts operating using the control program in the boot rom area. this mode is called the boot mode. the control program in the boot rom area can also be used to rewrite the user rom area. cpu rewrite mode operation procedure the internal flash memory can be operated on to program, read, verify, or erase it while being placed on- board by writing commands from the cpu to the flash memory control register (addresses 03b4 16 , 03b5 16 ) and flash command register (address 03b6 16 ). note that when in cpu rewrite mode, the boot rom area cannot be accessed for program, read, verify, or erase operations. before this can be accom- plished, a cpu write control program must be written into the boot rom area in parallel input/output mode. the following shows a cpu rewrite mode operation procedure. (1) apply v pp h to the cnv ss /v pp pin and v cc to the port p4 6 pin for reset release. or the user can jump from the user rom area to the boot rom area using the jmp instruction and execute the cpu write control program. in this case, set the cpu write mode select bit of the flash memory control register to 1 before applying v pp h to the cnv ss /v pp pin. (2) after transferring the cpu write control program from the boot rom area to the internal ram, jump to this control program in ram. (the operations described below are controlled by this program.) (3) set the cpu rewrite mode select bit to 1. (4) read the cpu rewrite mode monitor flag to see that the cpu rewrite mode is enabled. (5) execute operation on the flash memory by writing software commands to the flash command regis- ter. note 1: in addition to the above, various other operations need to be performed, such as for entering the data to be written to flash memory from an external source (e.g., serial i/o), initializing the ports, and writing to the watchdog timer. (1) apply v ss to the cnv ss /v pp pin. (2) set the cpu rewrite mode select bit to 0.
cpu rewrite mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 156 precautions on cpu rewrite mode described below are the precautions to be observed when rewriting the flash memory in cpu rewrite mode. (1) operation speed during erase/program mode, set bclk to one of the following frequencies by changing the divide ratio: 5 mhz or less when wait bit (bit 7 at address 0005 16 ) = 0 (without internal access wait state) 10 mhz or less when wait bit (bit 7 at address 0005 16 ) = 1 (with internal access wait state)(note 1) (2) instructions inhibited against use the instructions listed below cannot be used during cpu rewrite mode because they refer to the internal data of the flash memory: und instruction, into instruction, jmps instruction, jsrs instruction, and brk instruction (3) interrupts inhibited against use no interrupts can be used that look up the fixed vector table in the flash memory area. maskable interrupts may be used by setting the interrupt vector table in a location outside the flash memory area. note 1: internal access wait state can be set in cpu rewrite mode. in this time, the following function is only used. ? cpu, rom, ram, timer, uart, si/o2(non-automatic transfer), port in case of setting internal access wait state, refer to the following explain (software wait). software wait a software wait can be inserted by setting the wait bit (bit 7) of the processor mode register 1 (address 0005 16 ) (note 2). a software wait is inserted in the internal rom/ram area by setting the wait bit of the processor mode register 1. when set to 0, each bus cycle is executed in one bclk cycle. when set to 1, each bus cycle is executed in two bclk cycles. after the microcomputer has been reset, this bit defaults to 0. the sfr area is always accessed in two bclk cycles regardless of the setting of this control bit. table da-1 shows the software wait and bus cycles. figure da-6 shows example bus timing when using software waits. note 2: before attempting to change the contents of the processor mode register 1, set bit 1 of the protect register (address 000a 16 ) to 1. area wait bit bus cycle 1 2 bclk cycles sfr internal rom/ram 0 1 bclk cycle invalid 2 bclk cycles table da-1. software waits and bus cycles
cpu rewrite mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 157 figure da-6. typical bus timings using software wait output input address address bus cycle < internal bus (with wait) > bclk read signal write signal data bus address bus bclk read signal write signal address bus address address bus cycle < internal bus (no wait) > output data bus input
cpu rewrite mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 158 command program verify read program 03b6 16 first bus cycle second bus cycle 00 16 40 16 c0 16 write write write program address write read erase verify a0 16 write verify address verify data read erase 20 16 write 03b6 16 20 16 write verify address reset ff 16 write mode address mode address data (d 0 to d 7 ) data (d 0 to d 7 ) 03b6 16 03b6 16 03b6 16 03b6 16 03b6 16 program data verify data ff 16 write 03b6 16 software commands table bb-1 lists the software commands available with the m30218 group (flash memory version). when cpu rewrite mode is enabled, write software commands to the flash command register to specify the operation to erase or program. the content of each software command is explained below. table bb-1. list of software commands (cpu rewrite mode) read command (00 16 ) the read mode is entered by writing the command code 00 16 to the flash command register in the first bus cycle. when an address to be read is input in one of the bus cycles that follow, the content of the specified address is read out at the data bus (d 0 Cd 7 ), 8 bits at a time. the read mode is retained intact until another command is written. after reset and after the reset command is executed, the read mode is set. program command (40 16 ) the program mode is entered by writing the command code 40 16 to the flash command register in the first bus cycle. when the user execute an instruction to write byte data to the desired address (e.g., ste instruction) in the second bus cycle, the flash memory control circuit executes the program op- eration. the program operation requires approximately 20 m s. wait for 20 m s or more before the user go to the next processing. during program operation, the watchdog timer remains idle, with the value 7fff 16 set in it. note 1: the write operation is not completed immediately by writing a program command once. the user must always execute a program-verify command after each program command executed. and if verification fails, the user need to execute the program command repeatedly until the verification passes. see figure bb.3 for an example of a programming flowchart.
cpu rewrite mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 159 program-verify command (c0 16 ) the program-verify mode is entered by writing the command code c0 16 to the flash command register in the first bus cycle. when the user execute an instruction (e.g., lde instruction) to read byte data from the address to be verified (the previously programmed address) in the second bus cycle, the content that has actually been written to the address is read out from the memory. the cpu compares this read data with the data that it previously wrote to the address using the program command. if the compared data do not match, the user need to execute the program and program-verify operations one more time. erase command (20 16 + 20 16 ) the flash memory control circuit executes an erase operation by writing command code 20 16 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. the erase operation requires approximately 20 ms. wait for 20 ms or more before the user go to the next processing. before this erase command can be performed, all memory locations to be erased must have had data 00 16 written to by using the program and program-verify commands. during erase operation, the watchdog timer remains idle, with the value 7fff 16 set in it. note 1: the erase operation is not completed immediately by writing an erase command once. the user must always execute an erase-verify command after each erase command executed. and if verification fails, the user need to execute the erase command repeatedly until the verification passes. see figure bb-3 for an example of an erase flowchart. erase-verify command (a0 16 ) the erase-verify mode is entered by writing the command code a0 16 to the flash command register in the first bus cycle. when the user execute an instruction to read byte data from the address to be verified (e.g., lde instruction) in the second bus cycle, the content of the address is read out. the cpu must sequentially erase-verify memory contents one address at a time, over the entire area erased. if any address is encountered whose content is not ff 16 (not erased), the cpu must stop erase-verify at that point and execute erase and erase-verify operations one more time. note 1: if any unerased memory location is encountered during erase-verify operation, be sure to execute erase and erase-verify operations one more time. in this case, however, the user does not need to write data 00 16 to memory before erasing.
cpu rewrite mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 160 start address = first location loop counter : x=0 write program command write : 40 16 duration = 20 s duration = 6 s x=25 ? verify ok ? pass fail fail pass yes pass no no fail write program data/ address loop counter : x=x+1 write program verify command last address ? next address ? write read command write read command verify ok ? write : program data write : c0 16 write : 00 16 write:20 16 duration = 6s x=1000 ? verify ok? pass fail fail pass yes pass no no fail duration = 20ms yes no start all bytes = "00 16 "? program all bytes = "00 16 " address = first address loop counter x=0 write erase command write erase command loop counter x=x+1 write erase verify command/address verify ok? last address? next address write read command write read command write:20 16 write:a0 16 write:00 16 read: expect value=ff 16 figure bb-3. program and erase execution flowchart in the cpu rewrite mode program erase reset command (ff 16 + ff 16 ) the reset command is used to stop the program command or the erase command in the middle of operation. after writing command code 40 16 or 20 16 twice to the flash command register, write command code ff 16 to the flash command register in the first bus cycle and the same command code to the flash command register again in the second bus cycle. the program command or erase command is disabled, with the flash memory placed in read mode.
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 161 pin description v cc ,v ss apply 5v 10 % to vcc pin and 0 v to vss pin. cnv ss apply 12v 5 % to this pin. reset reset input pin. while reset is "l" level, a 20 cycle or longer clock must be input to xin pin. x in connect a ceramic resonator or crystal oscillator between x in and x out pins. to input an externally generated clock, input it to x in pin and open x out pin. x out av cc , av ss v ref connect av ss to vss and avcc to vcc, respectively. enter the reference voltage for ad from this pin. p0 0 to p0 7 output exclusive use pin. p1 0 to p1 7 output exclusive use pin. p2 0 to p2 7 output exclusive use pin. p3 0 to p3 7 input "h" or "l" level signal or open. p4 0 to p4 3 input "h" or "l" level signal or open. p4 4 serial data output pin. p4 5 p4 6 serial clock input pin. p4 7 p5 0 to p5 7 output exclusive use pin. name power input cnv ss reset input clock input clock output analog power supply input reference voltage input output port p0 output port p1 output port p2 input port p3 input port p4 txd output sclk input busy output output port p5 i/o i i i o i o o o i i i i o o rxd input serial data input pin. o busy signal output pin. p6 0 to p6 7 output exclusive use pin. p7 0 to p7 7 input "h" or "l" level signal or open. output port p6 input port p7 o i p8 0 to p8 7 input "h" or "l" level signal or open. input port p8 i p9 0 to p9 7 input "h" or "l" level signal or open. input port p9 i p10 0 to p10 7 input "h" or "l" level signal or open. input port p10 i pin functions (flash memory standard serial i/o mode)
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 162 figure dd-1. pin connections for serial i/o mode (1) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 1 00 m30218fcfp p6 0 /fld0 p6 1 /fld1 p6 2 /fld2 p6 3 /fld3 p6 4 /fld4 p6 5 /fld5 p6 6 /fld6 p6 7 /fld7 p5 0 /fld8 v cc x in reset x out v ss cnv ss p8 6 /x cout p8 7 /x cin p9 0 /srdy2 p7 6 /ta3 in /ta1 out /clk1 p7 7 /ta4 in /ta2 out /cts1/rts1/clks1 p9 4 /s out 2 p9 5 /sclk21 p9 6 /da1/sclk22 p9 7 /da0/clk out /dim out p9 2 /sstb2 p9 3 /s in2 p7 3 /ta0 in /ta3 out p7 2 /tb2 in p9 1 /sbusy2 v ee p10 7 /an7 p10 6 /an6 p10 5 /an5 p10 3 /an3 p10 2 /an2 p10 4 /an4 p10 1 /an1 av ss p10 0 /an0 v ref av cc p5 1 /fld9 p5 2 /fld10 p5 3 /fld11 p5 4 /fld12 p5 5 /fld13 p5 6 /fld14 p5 7 /fld15 p0 0 /fld16 p0 1 /fld17 p0 2 /fld18 p0 3 /fld19 p0 4 /fld20 p0 5 /fld21 p0 6 /fld22 v ss p0 7 /fld23 v cc p1 0 /fld24 p1 1 /fld25 p1 2 /fld26 p1 3 /fld27 p1 4 /fld28 p1 5 /fld29 p1 6 /fld30 p1 7 /fld31 p2 0 /fld32 p2 1 /fld33 p2 2 /fld34 p2 3 /fld35 p2 4 /fld36 p2 5 /fld37 p2 6 /fld38 p2 7 /fld39 p3 0 /fld40 p3 1 /fld41 p3 2 /fld42 p3 3 /fld43 p3 4 /fld44 p3 5 /fld45 p3 6 /fld46 p3 7 /fld47 p4 0 /fld48 p4 1 /fld49 p4 2 /fld50 p4 3 /fld51 p4 4 /t x d0/fld52 p4 5 /r x d0/fld53 p4 6 /clk0/fld54 p47/cts0/rts0/fld55 p7 5 /ta2 in /ta0 out /r x d1 p7 4 /ta1 in /ta4 out /t x d1 p7 1 /tb1 in p7 0 /tb0 in p8 5 /int5 p8 4 /int4 p8 3 /int3 p8 2 /int2 p8 1 /int1 p8 0 /int0 vss vcc cnvss vss vcc cnvss vpph reset txd sclk rxd busy reset vss vcc mode setup method signal value v ss v cc connect oscillator circuit.
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 163 standard serial i/o mode the standard serial i/o mode serially inputs and outputs the software commands, addresses and data necessary for operating (read, program, erase, etc.) the internal flash memory. it uses a purpose-specific serial programmer. the standard serial i/o mode differs from the parallel i/o mode in that the cpu controls operations like rewriting (uses the cpu rewrite mode) in the flash memory or serial input for rewriting data. the standard serial i/o mode is started by clearing the reset with v pph at the cnvss pin. (for the normal microprocessor mode, set cnvss to l.) this control program is written in the boot rom area when shipped from mitsubishi electric. therefore, if the boot rom area is rewritten in the parallel i/o mode, the standard serial i/o mode cannot be used. figures dd-1 shows the pin connections for the standard serial i/o mode. serial data i/o uses three uart0 pins: clk 0 , rxd 0 , txd 0 , and rts 0 (busy). the clk 0 pin is the transfer clock input pin and it transfers the external transfer clock. the txd 0 pin outputs the cmos signal. the rts 0 (busy) pin outputs an l level when reception setup ends and an h level when the reception operation starts. transmission and reception data is transferred serially in 8-byte blocks. in the standard serial i/o mode, only the user rom area shown in figure aa-3 can be rewritten, the boot rom area cannot. the standard serial i/o mode has a 7-byte id code. when the flash memory is not blank and the id code does not match the content of the flash memory, the command sent from the programmer is not accepted. function overview (standard serial i/o mode) in the standard serial i/o mode, software commands, addresses and data are input and output between the flash memory and an external device (serial programmer, etc.) using a clock synchronized serial i/o (uart0) . in reception, the software commands, addresses and program data are synchronized with the rise of the transfer clock input to the clk 0 pin and input into the flash memory via the rxd 0 pin. in transmission, the read data and status are synchronized with the fall of the transfer clock and output to the outside from the txd 0 pin. the txd 0 pin is cmos output. transmission is in 8-bit blocks and lsb first. when busy, either during transmission or reception, or while executing an erase operation or program, the rts 0 (busy) pin is h level. accordingly, do not start the next transmission until the rts 0 (busy) pin is l level. also, data in memory and the status register can be read after inputting a software command. it is pos- sible to check flash memory operating status or whether a program or erase operation ended success- fully or in error by reading the status register. software commands and the status register are explained here following.
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 164 software commands table dd-1 lists software commands. in the standard serial i/o mode, erase operations, programs and reading are controlled by transferring software commands via the rxd pin. software commands are explained here below. table dd-1. software commands (standard serial i/o mode) control command 2nd byte 3rd byte 4th byte 5th byte 6th byte 1 page read 2 page program 3 bclock ease 4 erase all unlocked blocks 5 read status register 6 clear status register 7 read lockbit status 8 id check function 9 download function 10 version data output function 11 boot area output function note1: shading indicates transfer from flash memory microcomputer to serial programmer. all other data is transferred from the serial programmer to the flash memory microcomputer. note2: srd refers to status register data. srd1 refers to status register 1 data. note3: all commands can be accepted when the flash memory is totally blank. when id is not verificate not acceptable not acceptable not acceptable not acceptable acceptable not acceptable not acceptable acceptable not acceptable acceptable not acceptable version data output to 9th byte data output to 259th byte data output to 259th byte data input to 259th byte to id7 data output data input id1 to required number of times version data output data output data output data input id size data input version data output data output data output data input d0 16 lock bit data output address (high) check- sum version data output data output address (high) address (high) address (high) srd1 output address (high) address (middle) size (high) version data output address (high) address (middle) address (middle) address (middle) d0 16 srd output address (middle) address (low) size (low) version data output address (middle) ff 16 41 16 20 16 a7 16 70 16 50 16 71 16 f5 16 fa 16 fb 16 fc 16 1st byte transfer
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 165 page read command this command reads the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page read command as explained here following. (1) send the ff 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first in sync with the rise of the clock. data0 data255 clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 ff 16 srd output srd1 output clk0 rxd0 txd0 rts0(busy) 70 16 figure dd-2. timing for page read read status register command this command reads status information. when the 70 16 command code is sent in the 1st byte of the transmission, the contents of the status register (srd) specified in the 2nd byte of the transmission and the contents of status register 1 (srd1) specified in the 3rd byte of the transmission are read. figure dd-3. timing for reading the status register
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 166 figure dd-4. timing for clearing the status register page program command this command writes the specified page (256 bytes) in the flash memory sequentially one byte at a time. execute the page program command as explained here following. (1) send the 41 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respectively. (3) from the 4th byte onward, as write data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 is input sequentially from the smallest address first, that page is automatically written. when reception setup for the next 256 bytes ends, the rts 0 (busy) signal changes from the h to the l level. the result of the page program can be known by reading the status register. for more information, see the section on the status register. clk0 rxd0 txd0 rts0(busy) 50 16 clear status register command this command clears the bits (sr3Csr4) which are set when the status register operation ends in error. when the 50 16 command code is sent in the 1st byte of the transmission, the aforementioned bits are cleared. when the clear status register operation ends, the rts 0 (busy) signal changes from the h to the l level. clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 41 16 data0 data255 figure dd-5. timing for the page program
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 167 block erase command this command erases the data in the specified block. execute the block erase command as explained here following. (1) send the 20 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) send the verify command code d0 16 in the 4th byte of the transmission. with the verify com- mand code, the erase operation will start for the specified block in the flash memory. write the highest address of the specified block for addresses a 16 to a 23 . when block erasing ends, the rts0 (busy) signal changes from the h to the l level. after block erase ends, the result of the block erase operation can be known by reading the status register. for more information, see the section on the status register. each block can be erase-protected with the lock bit. for more information, see the section on the data protection function. figure dd-6.timing for block erasing a 8 to a 15 a 16 to a 23 20 16 d0 16 clk0 rxd0 txd0 rts0(busy)
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 168 read lock bit status command this command reads the lock bit status of the specified block. execute the read lock bit status com- mand as explained here following. (1) send the 71 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) the lock bit data of the specified block is output in the 4th byte of the transmission. write the highest address of the specified block for addresses a 8 to a 23 . the m30218 group (flash memory version) does not have the lock bit, so the read value is always 1 (block unlock). clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 71 16 dq6 figure dd-8. timing for reading lock bit status erase all unlocked blocks command this command erases the content of all blocks. execute the erase all unlocked blocks command as explained here following. (1) send the a7 16 command code in the 1st byte of the transmission. (2) send the verify command code d0 16 in the 2nd byte of the transmission. with the verify com- mand code, the erase operation will start and continue for all blocks in the flash memory. when block erasing ends, the rts 0 (busy) signal changes from the h to the l level. the result of the erase operation can be known by reading the status register. clk0 rxd0 txd0 rts0(busy) a7 16 d0 16 figure dd-7. timing for erasing all unlocked blocks
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 169 download command this command downloads a program to the ram for execution. execute the download command as explained here following. (1) send the fa 16 command code in the 1st byte of the transmission. (2) send the program size in the 2nd and 3rd bytes of the transmission. (3) send the check sum in the 4th byte of the transmission. the check sum is added to all data sent in the 5th byte onward. (4) the program to execute is sent in the 5th byte onward. when all data has been transmitted, if the check sum matches, the downloaded program is executed. the size of the program will vary according to the internal ram. fa 16 program data program data data size (high) data size (low) check sum clk0 rxd0 txd0 rts0(busy) figure dd-9. timing for download
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 170 version information output command this command outputs the version information of the control program stored in the boot area. execute the version information output command as explained here following. (1) send the fb 16 command code in the 1st byte of the transmission. (2) the version information will be output from the 2nd byte onward. this data is composed of 8 ascii code characters. figure dd-10. timing for version information output boot area output command this command outputs the control program stored in the boot area in one page blocks (256 bytes). execute the boot area output command as explained here following. (1) send the fc 16 command code in the 1st byte of the transmission. (2) send addresses a 8 to a 15 and a 16 to a 23 in the 2nd and 3rd bytes of the transmission respec- tively. (3) from the 4th byte onward, data (d 0 Cd 7 ) for the page (256 bytes) specified with addresses a 8 to a 23 will be output sequentially from the smallest address first, in sync with the rise of the clock. fb 16 'x' 'v' 'e' 'r' clk0 rxd0 txd0 rts0(busy) data0 data255 clk0 rxd0 txd0 rts0(busy) a 8 to a 15 a 16 to a 23 fc 16 figure dd-11. timing for boot area output
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 171 id check this command checks the id code. execute the boot id check command as explained here following. (1) send the f5 16 command code in the 1st byte of the transmission. (2) send addresses a 0 to a 7 , a 8 to a 15 and a 16 to a 23 of the 1st byte of the id code in the 2nd, 3rd and 4th bytes of the transmission respectively. (3) send the number of data sets of the id code in the 5th byte. (4) the id code is sent in the 6th byte onward, starting with the 1st byte of the code. id size id1 id7 clk0 rxd0 txd0 rts0(busy) f5 16 df 16 ff 16 0f 16 figure dd-12. timing for the id check id code when the flash memory is not blank, the id code sent from the serial programmer and the id code written in the flash memory are compared to see if they match. if the codes do not match, the com- mand sent from the serial programmer is not accepted. an id code contains 8 bits of data. area is, from the 1st byte, addresses 0fffdf 16 , 0fffe3 16 , 0fffeb 16 , 0fffef 16 , 0ffff3 16 , and 0ffff7 16 . write a program into the flash memory, which already has the id code set for these addresses. reset vector watchdog timer vector single step vector address match vector brk instruction vector overflow vector undefined instruction vector id7 id6 id5 id4 id3 id2 id1 dbc vector 0fffff 16 to 0ffffc 16 0ffffb 16 to 0ffff8 16 0ffff7 16 to 0ffff4 16 0ffff3 16 to 0ffff0 16 0fffef 16 to 0fffec 16 0fffeb 16 to 0fffe8 16 0fffe7 16 to 0fffe4 16 0fffe3 16 to 0fffe0 16 0fffdf 16 to 0fffdc 16 4 bytes address figure dd-13. id code storage addresses
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 172 status register (srd) the status register indicates operating status of the flash memory and status such as whether an erase operation or a program ended successfully or in error. it can be read by writing the read status register command (70 16 ). also, the status register is cleared by writing the clear status register command (50 16 ). table dd-2 gives the definition of each status register bit. after clearing the reset, the status register outputs 80 16 . table dd-2. status register (srd) status bit (sr7) the status bit indicates the operating status of the flash memory. when power is turned on, 1 (ready) is set for it. the bit is set to 0 (busy) during an auto write or auto erase operation, but it is set back to 1 when the operation ends. erase bit (sr5) the erase bit reports the operating status of the auto erase operation. if an erase error occurs, it is set to 1. when the erase status is cleared, it is set to 0. program bit (sr4) the program bit reports the operating status of the auto write operation. if a write error occurs, it is set to 1. when the program status is cleared, it is set to 0. srd0 bits sr7 (bit7) sr6 (bit6) sr5 (bit5) sr4 (bit4) sr3 (bit3) sr2 (bit2) sr1 (bit1) sr0 (bit0) status name status bit reserved erase bit program bit reserved reserved reserved reserved definition "1" "0" ready - terminated in error terminated in error - - - - busy - terminated normally terminated normally - - - -
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 173 status register 1 (srd1) status register 1 indicates the status of serial communications, results from id checks and results from check sum comparisons. it can be read after the srd by writing the read status register command (70 16 ). also, status register 1 is cleared by writing the clear status register command (50 16 ). table dd-3 gives the definition of each status register 1 bit. 00 16 is output when power is turned on and the flag status is maintained even after the reset. table dd-3. status register 1 (srd1) boot update completed bit (sr15) this flag indicates whether the control program was downloaded to the ram or not, using the down- load function. check sum consistency bit (sr12) this flag indicates whether the check sum matches or not when a program, is downloaded for execu- tion using the download function. id check completed bits (sr11 and sr10) these flags indicate the result of id checks. some commands cannot be accepted without an id check. data reception time out (sr9) this flag indicates when a time out error is generated during data reception. if this flag is attached during data reception, the received data is discarded and the microcomputer returns to the command wait state. srd1 bits sr15 (bit7) sr14 (bit6) sr13 (bit5) sr12 (bit4) sr11 (bit3) sr10 (bit2) sr9 (bit1) sr8 (bit0) status name boot update completed bit reserved reserved checksum match bit id check completed bits data receive time out reserved definition "1" "0" update completed - - match 00 01 10 11 not update - - mismatch normal operation - not verified verification mismatch reserved verified time out -
appendix standard serial i/o mode under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 174 example circuit application for the standard serial i/o mode the below figure shows a circuit application for the standard serial i/o mode. control pins will vary ac- cording to programmer, therefore see the programmer manual for more information. rts0(busy) clk0 r x d0 t x d0 cnvss clock input rts output data input data output m30218 flash memory version (1) control pins and external circuitry will vary according to programmer. for more information, see the programmer manual. (2) in this example, the microprocessor mode and standard serial i/o mode are switched via a switch. v pp figure dd-14. example circuit application for the standard serial i/o mode
contents for change revision date version revision history m30218 data sheet under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 175 rev.a1 99.12.21 revision history page 2 figure aa-1 m30218- xxxfp ---> m30218- xxxxfp page 10 figure ba-3 03b8 16 dma0 cause select register ---> dma0 request cause select register 03ba 16 dma1 cause select register ---> dma1 request cause select register page 55 figure ka-2 fldc mode register bit3, bit2 (at rising edge of each edge) ---> (at rising edge of each digit) 1 1: ---> 1 0: page 90 figure ga-4 uarti transmit/receive control register 0 bit4 (p4 7 and p7 4 function as) ---> (p4 7 and p7 7 function as) page 128 exclusive high-breakdown]voltage output ports line 2 all ports have structure of high-breakdown-voltage p-channel open drain output and pull-down resistance. ---> all ports have structure of high-breakdown-voltage p-channel open drain output. exclusive output ports except p2 have built-in pull- down resistance. page 134 add to note 3.
contents for change revision date version revision history m30218 data sheet under development preliminary specifications rev.a1 specifications in this manual are tentative and subject to change. mitsubishi microcomputers m30218 group single-chip 16-bit cmos microcomputer 176
mitsubishi semiconductors m30218 group specification rev.a1 dec. first edition 1999 editioned by committee of editing of mitsubishi semiconductor published by mitsubishi electric corp., kitaitami works this book, or parts thereof, may not be reproduced in any form without permission of mitsubishi electric corporation. ?1999 mitsubishi electric corporation

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